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參數資料
| 型號： | PE3293 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 1.8GHz/550MHz Dual Fractional-N Ultra-Low Spurious PLL for Frequency Synthesis |
| 中文描述： | 1.8GHz/550MHz雙分數N超低的雜散鎖相環(huán)頻率合成 |
| 文件頁數： | 12/18頁 |
| 文件大?。?/td> | 266K |
| 代理商： | PE3293 |
PE3293
Product Specification
Phase Comparator Characteristics
Copyright
Peregrine Semiconductor Corp. 2003
Page 12 of 18
File No. 70/0015~02C
|
UTSi
CMOS RFIC SOLUTIONS
PLL1 has the timing relationships shown below for f
c
1, f
p
1, LD1, UP1, and DOWN1. When C
11
= HIGH, UP1
directs the internal PLL1 charge pump to source current and DOWN1 directs the PLL1 internal charge pump to
sink current. If C
11
= LOW, UP1 and DOWN1 are interchanged.
PLL2 has the timing relationships shown below for f
c
2, f
p
2, LD2, UP2, and DOWN2. When C
21
= HIGH, UP2
directs the internal PLL2 charge pump to source current and DOWN2 directs the PLL2 internal charge pump to
sink current. If C
21
= LOW, UP2 and DOWN2 are interchanged.
Figure 7. Phase Comparator Timing Diagram
Note 1:
f
c
1(2), f
p
1(2), and LD1(2) are accessible via the f
o
LD pin per programming in Table 11.
f
c
1 (2)
(Note 1)
f
p
1 (2)
(Note 1)
LD1 (2)
(Note 1)
UP1 (2)
DOWN1 (2)
f
c
leads f
p
f
c
= f
p
f
c
lags f
p
f
c
lags f
p
f
c
lags f
p
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