參數(shù)資料
型號(hào): PDI1394P11A
廠商: NXP Semiconductors N.V.
英文描述: 3-port physical layer interface
中文描述: 三端口物理層接口
文件頁數(shù): 2/20頁
文件大?。?/td> 135K
代理商: PDI1394P11A
Philips Semiconductors
Preliminary specification
PDI1394P11A
3-port physical layer interface
2
1999 Mar 10
1.0
3 cable interface ports
Supports 100Mb/s and 200Mb/s transfers
Interfaces to any 1394 standard Link Layer Controller
5V tolerant I/Os with Bus Hold Circuitry
Single 3.3V supply voltage
Arbitrated (short) Bus Reset (1394a feature)
Fully compatible with existing 100 Mbps Phys on the market
Prevents a TpBias voltage driven into a non-powered
PDI1394P11A from erroneously powering up the part
FEATURES
2.0
The Philips Semiconductors PDI1394P11A is an IEEE1394-1995
compliant Physical Layer interface. The PDI1394P11A provides the
analog physical layer functions needed to implement a three port
node in a cable-based IEEE 1394–1995 network. Additionally, the
device manages bus initialization and arbitration cycles, as well as
transmission and reception of data bits. The Link Layer Controller
interface is compatible with both 3V and 5V Link Controllers. While
providing a maximum transmission data rate of 200 Mb/s, the
PDI1394P11A is compatible with current 100 Mb/s Physical Layer
ICs. The PDI1394P11A is available in the LQFP64 package.
DESCRIPTION
3.0
ORDERING INFORMATION
PACKAGE
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
64-pin plastic LQFP
0
°
C to +70
°
C
PDI1394P11A BD
PD1394P11A BD
SOT314-2
4.0
PIN CONFIGURATION
SV01073
TPBIAS3
TPBIAS2
TPBIAS1
TPA1+
TPA1–
TPB1+
TPB1–
AGND
TPA2+
TPA2–
TPB2+
TPB2–
TPA3+
TPA3–
TPB3+
TPB3–
D
D
I
A
R
R
P
X
X
F
P
P
A
A
RESET–
LPS
PD
DGND
SYSCLK
DGND
CTL0
CTL1
D0
D1
D2
D3
D
D
D
T
T
C
A
C
P
P
P
C
A
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
4
1
1
1
2
2
2
2
2
2
2
2
2
2
3
3
3
PDI1394P11A
DVDD
DVDD
DVDD
LREQ
D
A
A
A
A
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