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參數(shù)資料
| 型號： | PDI1394P11A |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 3-port physical layer interface |
| 中文描述： | 三端口物理層接口 |
| 文件頁數(shù)： | 13/20頁 |
| 文件大?。?/td> | 135K |
| 代理商： | PDI1394P11A |
Philips Semiconductors
Preliminary specification
PDI1394P11A
3-port physical layer interface
1999 Mar 10
13
18.0
EXTERNAL COMPONENTS AND CONNECTIONS
18.1
Forcing this pin low causes a Bus Reset condition on the active
cable ports, and resets the internal logic to the Reset Start state.
SYSCLK remains active. For power up (and after power down is
asserted) a 2 ms delay is required to assure proper PLL operation.
An internal pull-up resistor is connected to V
DD
, so only an external
delay capacitor is required. This input is a standard logic buffer and
may also be driven by an open drain logic output buffer. The RESET
pin also has a n-channel pull-down transistor activated by the Power
Down pin. For a reset during normal operation, a 10 s low pulse on
this pin will accomplish a full PHY reset. This pulse as well as the
2 ms power up pulse could be microprocessor controlled in which
case the external delay capacitor would not be needed. For more
details on using single capacitor isolation with this pin please refer to
the Philips Isolation Application Note AN2452.
Logic Reset input (RESET–, pin 1)
18.2
In a non-isolated implementation a 10k
resistor is connected to the
V
DD
supplying the link layer controller to monitor the link’s power
status. In an isolated implementation a square wave with a minimum
frequency of 500 kHz can be applied to the LPS pin to indicate the
pin is powered. If the link is not powered on, the Control I/O’s (pins
11,12), Data I/O’s (pins 13 – 16) and SYSCLK output (pin 9) are
disabled, and the PDI1394P11A will perform only the basic repeater
functions required for network initialization and operation. This pin is
equipped with Bus Hold circuitry.
Link Power Status input (LPS, pin 2)
18.3
LREQ is a signal from the link layer controller used to request the
PDI1394P11A to perform some service. This pin is equipped with
Bus Hold circuitry and supports an optional isolation barrier.
Link Request input (LREQ, pin 3)
18.4
This input powers down all device functions with the exception of the
CNA circuit to conserve power in portable or battery powered
applications. It must be held high for at least 3.5ms to assure a
successful reset after power down. This pin is equipped with Bus
Hold circuitry and supports an optional isolation barrier.
Power Down input (PD, pin 7)
18.5
Provides a 49.152 MHz clock signal, synchronized with the data
transfers, to the link layer controller. This pin supports an optional
isolation barrier.
System Clock output (SYSCLK, pin 9)
18.6
These are bi-directional signals used in the communication between
the PDI1394P11A and the link layer controller that control passage
of information between the two devices. These pins are equipped
with Bus Hold circuitry and support an optional isolation barrier.
Control I/Os (CTL[0:1], pins[11,12])
18.7
These are bi-directional information signals used in the
communication between the PDI1394P11A and the link layer
controller. These pins are equipped with Bus Hold circuitry and
support an optional isolation barrier.
Data I/Os (D[0:3], pins [13,14,15,16])
18.8
(TESTM[1:2], pins[22,21])
These two logic signals are used in manufacturing to enable
production line testing of the PDI1394P11A. For normal use these
should be tied to V
DD
. To enable ISBR (Arbitrated (short) bus reset)
mode, set TESTM1 high and TESTM2 low. See section 17.1 for
more information on ISBR mode.
Test Mode control and ISBR mode inputs
18.9
This is normally connected to the cable power through an external
resistor. The circuit drives an internal comparator which is used to
detect the presence of cable power. This information is maintained
in an internal register and is available to the link layer controller
through a register read. See section 17.2 for information on setting
the CPS trip point.
Cable Power Status input (CPS, pin 23)
18.10
Capable input or Link-On output (C/LKON, pin 27)
On hardware reset, this pin is used to set the default value of the
contender status indicated during self-ID. The bit value programming
is done by tying the pin through a 10 k resistor to V
DD
(high, bus
manager capable) or to GND (low, not bus manager capable). Using
either a pull-up or pull-down resistor allows the link-on output to
override the input value when necessary. After hardware reset, this
pin is used as an output to signal the reception of a Link-On packet.
A 6.114 MHz signal is supplied until the LPS input is active at which
point the C/LKON output goes low.
Bus or Isochronous Resource Manager
18.11
(PC[0:2], pins [30,29,28])
Used as inputs to set the bit values of the three Power Class bits in
the self-ID packet (bits 21, 22 and 23). These bits can be
programmed by tying the pins high to V
DD
or low to GND.
Power Class bits 0 through 2 inputs
18.12
This pin outputs the cable connection status. If all ports are
disconnected this pin outputs a high. If any port has a cable
connected then this pin outputs a low.
Cable Not Active output (CNA, pin 31)
18.13
pins [45, 40, 36], TPA[1:3]–, pins [44,39,35],
TPB[1:3]+, pins [43,38,34], TPB[1:3]–,
pins [42, 37, 33])
These pins send and receive differential data over the twisted pair
cables. Two series connected external 56
cable termination
resistors are required at each twisted pair. Each unused TPB pin
must be tied through a 5k
resistor to ground. The TPA pins can be
left floating.
Twisted Pair I/O’s (TPA[1:3]+,
18.14
pins [46, 47, 48])
These outputs provide the 1.86 V nominal bias voltage needed for
proper operation of the twisted pair cable drivers, and for signaling
to the remote nodes that there is a valid cable connection. Three
TPBIAS outputs are provided for separate connection to each of the
three TPA twisted pairs to provide electrical isolation. A 1
μ
F
capacitor to ground must be connected to each TPBIAS pin whether
it is used or not.
Twisted Pair Bias outputs (TPBIAS[1:3],
18.15
This pin is connected to an external filter capacitor used in a lag-lead
filter for a PLL frequency multiplier running off of the crystal oscillator.
PLL Filter (FILTER, pin 54)
18.16
These pins connect to a 24.576 MHz parallel resonant fundamental
mode crystal. The optimum values for the external shunt capacitors
are dependent on the specifications of the crystal used, the suggested
values of 12 pF are appropriate for one specified for 15 pF loads.
Oscillator crystal (Xl, pin 56 & XO, pin 57)
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