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參數(shù)資料
| 型號： | PCX7447AVGH1167NB |
| 廠商： | Atmel |
| 文件頁數(shù)： | 38/52頁 |
| 文件大小： | 0K |
| 描述： | IC MPU 32BIT 1167MHZ 360CBGA |
| 標準包裝： | 44 |
| 處理器類型： | PowerPC 32-位 RISC |
| 速度： | 1.167GHZ |
| 電壓： | 1.1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 360-CBBGA 裸露焊盤 |
| 供應商設備封裝： | 360-CBGA（25x25） |
| 包裝： | 托盤 |
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43
0833E–HIREL–01/07
e2v semiconductors SAS 2007
PC7447A
12.6
Pull-up/Pull-down Resistor Requirements
The PC7447A requires high-resistive (weak: 4.7-K
) pull-up resistors on several control pins of the bus
interface to maintain the control signals in the negated state after they have been actively negated and
released by the PC7447A or other bus masters. These pins are: TS, ARTRY, SHDO, and SHD1.
Some pins designated as being factory test pins must be pulled up to OV
DD or down to GND to ensure
proper device operation. For the PC7447A, 360 BGA, the pins that must be pulled up to OV
DD are
LSSD_MODE and TEST[0:3]; the pins that must be pulled down to GND are: L1_TSTCLK and TEST[4].
The CKSTP_IN signal should likewise be pulled up through a pull-up resistor (weak or stronger: 4.7–1
K
) to prevent erroneous assertions of this signal.
In addition, the PC7447A has one open-drain style output that requires a pull-up resistor (weak or stron-
ger: 4.7–1 K
) if it is used by the system. This pin is CKSTP_OUT.
If pull-down resistors are used to configure BVSEL, the resistors should be less than 250
(see Table 8-
1 on page 21). Because PLL_CFG[0:4] must remain stable during normal operation, strong pull-up and
pull-down resistors (1 K
or less) are recommended to configure these signals in order to protect
against erroneous switching due to ground bounce, power supply noise or noise coupling.
During inactive periods on the bus, the address and transfer attributes may not be driven by any master
and may, therefore, float in the high-impedance state for relatively long periods of time. Because the
PC7447A must continually monitor these signals for snooping, this float condition may cause excessive
power draw by the input receivers on the PC7447A or by other receivers in the system. These signals
can be pulled up through weak (10-K
) pull-up resistors by the system, address bus driven mode
enabled (see the MPC7450 RISC Microprocessor Family Users’ Manual for more information on this
mode), or they may be otherwise driven by the system during inactive periods of the bus to avoid this
additional power draw. Preliminary studies have shown the additional power draw by the PC7447A input
receivers to be negligible and, in any event, none of these measures are necessary for proper device
operation. The snooped address and transfer attribute inputs are: A[0:35], AP[0:4], TT[0:4], CI, WT, and
GBL.
If address or data parity is not used by the system, and respective parity checking is disabled through
HID1, the input receivers for those pins are disabled and do not require pull-up resistors, and may be left
unconnected by the system. If extended addressing is not used (HID0[XAEN] = 0), A[0:3] are unused
and must be pulled low to GND through weak pull-down resistors; additionally, if address parity checking
is enabled (HID1[EBA] = 1) and extended addressing is not used, AP[0] must be pulled up to OV
DD
through a weak pull-up resistor. If the PC7447A is in 60x bus mode, DTI[0:3] must be pulled low to GND
through weak pull-down resistors. The data bus input receivers are normally turned off when no read
operation is in progress and, therefore, do not require pull-up resistors on the bus. Other data bus receiv-
ers in the system, however, may require pull-ups, or that those signals be otherwise driven by the
system during inactive periods by the system. The data bus signals are: D[0:63] and DP[0:7].
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