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參數(shù)資料
| 型號： | PCM3002 |
| 英文描述： | 16-/20-Bit Single-Ended Analog Input/Output SoundPlus8482， |
| 中文描述： | 16-/20-Bit單端模擬輸入/輸出SoundPlus8482， |
| 文件頁數(shù)： | 21/23頁 |
| 文件大小： | 337K |
| 代理商： | PCM3002 |
21
PCM3002/3003
PCM3003 DATA FORMAT CONTROL
PCM3003 has hardwire functional control using PDAD (pin
7) and PDDA (pin 8) for Power-Down Control, DEM0 (pin
18) and DEM1 (pin 17) for de-emphasis and 20BIT (pin 16)
for 16-/20-bit format selection.
Power-Down Control (Pin 7 and Pin 8)
Both the ADC’s and DAC’s Power-Down Control pins
place the ADC or DAC section in the lowest power con-
sumption mode. The ADC/DAC operation is stopped by
cutting the supply current to the ADC/DAC section. DOUT
is fixed to zero during ADC Power-Down Mode enable and
V
OUT
is fixed to GND during DAC Power-Down Mode
enable. Figure 7 illustrates the ADC and DAC output re-
sponse for Power-Down ON/OFF. This does not affect the
ADC or DAC operation.
PDAD
PDDA
POWER DOWN
Low
Low
High
High
Low
High
Low
High
Reset (ADC/DAC Power-Down Enable)
ADC Power-Down/DAC Operate
ADC Operate/DAC Power-Down
ADC and DAC Normal Operation
De-Emphasis Control (Pin 17 and Pin 18)
DEM0 (pin 18) and DEM1 (pin 17) are used as de-emphasis
control pins.
DEM1
DEM0
DE-EMPHASIS
Low
Low
High
High
Low
High
Low
High
De-Emphasis Enable at 44.1kHz
De-Emphasis Disable
De-Emphasis Enable at 48kHz
De-Emphasis Enable at 32kHz
20BIT Audio Data Selection (Pin 16)
20BIT
FORMAT
Low
ADC: 16-bit MSB-first, Left-justified
DAC: 16-bit MSB-first, Right-justified
ADC: 20-bit MSB-first, Left-justified
DAC: 20-bit MSB-first, Right-justified
High
APPLICATION AND LAYOUT
CONSIDERATIONS
POWER SUPPLY BYPASSING
The digital and analog power supply lines to PCM3002/
3003 should be bypassed to the corresponding ground pins
with both 0.1
μ
F ceramic and 10
μ
F tantalum capacitors as
close to the device pins as possible. Although PCM3002/
3003 has three power supply lines to optimize dynamic
performance, the use of one common power supply is
generally recommended to avoid unexpected latch-up or pop
noise due to power supply sequencing problems. If separate
power supplies are used, back-to-back diodes are recom-
mended to avoid latch-up problems.
GROUNDING
In order to optimize the dynamic performance of PCM3002/
3003, the analog and digital grounds are not connected
internally. The PCM3002/3003 performance is optimized
with a single ground plane for all returns. It is recommended
to tie all PCM3002/3003 ground pins with low impedance
connections to the analog ground plane. PCM3002/3003
should reside entirely over this plane to avoid coupling high
frequency digital switching noise into the analog ground
plane.
VOLTAGE INPUT PINS
A tantalum capacitor, between 1
μ
F and 10
μ
F, is recom-
mended as an AC-coupling capacitor at the inputs. Combined
with the 30k
characteristic input impedance, a 1.0
μ
F cou-
pling capacitor will establish a 5.3Hz cut-off frequency for
blocking DC. The input voltage range can be increased by
adding a series resistor on the analog input line. This series
resistor, when combined with the 30k
input impedance,
creates a voltage divider and enables larger input ranges.
V
REF
INPUTS
A 4.7
μ
F to 10
μ
F tantalum capacitor is recommended be-
tween V
REF
L, V
REF
R, and AGND1 to ensure low source
impedance for the ADC’s references. These capacitors should
be located as close as possible to the reference pins to reduce
dynamic errors on the ADC reference.
V
COM
INPUTS
A 4.7
μ
F to 10
μ
F tantalum capacitor is recommended be-
tween V
COM
and AGND1 to ensure low source impedance
of the ADC and DAC common voltage. This capacitor
should be located as close as possible to the V
COM
pin to
reduce dynamic errors on the DAC common.
SYSTEM CLOCK
The quality of the system clock can influence dynamic
performance of both the ADC and DAC in the PCM3002/
3003. The duty cycle and jitter at the system clock input pin
must be carefully managed. When power is supplied to the
part, the system clock, bit clock (BCKIN) and a word clock
(LCRIN) should also be supplied simultaneously. Failure to
supply the audio clocks will result in a power dissipation
increase of up to three times normal dissipation and may
degrade long term reliability if the maximum power dissipa-
tion limit is exceeded.
RST CONTROL
If the capacitance between V
REF
and V
COM
exceeds 2.2
μ
F,
an external reset control delay time circuit must be used.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCM3002/PCM3003 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM3002. PCM3003 - 16-/20-Bit Single-Ended Analog Input/Output SoundPlus STEREO AUDIO CODECs |
| PCM3002_07 | 制造商:BB 制造商全稱:BB 功能描述:16/20-BIT SINGLE-ENDED ANALOG INPUT/OUTPUT STEREO AUDIO CODECS |
| PCM3002E | 功能描述:接口—CODEC 16/20-Bit Sngl-end Anlg I/O Ster Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| PCM3002E | 制造商:Texas Instruments 功能描述:AUDIO CODEC IC 制造商:Texas Instruments 功能描述:IC, AUDIO CODEC, 20BIT, 48KHZ, SSOP-24 |
| PCM3002E/2K | 功能描述:接口—CODEC 16/20-Bit Sngl-end Anlg I/O Ster Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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