參數(shù)資料
型號: PCM3002
英文描述: 16-/20-Bit Single-Ended Analog Input/Output SoundPlus8482,
中文描述: 16-/20-Bit單端模擬輸入/輸出SoundPlus8482,
文件頁數(shù): 20/23頁
文件大?。?/td> 337K
代理商: PCM3002
PCM3002/3003
20
LOP:
Bit 5
When this bit is set to “1”, the ADC’s audio data
is sent directly to the DAC. The data format will
default to I
2
S. In Format 3 (I
2
S Frame), Loop-
back is not supported.
ADC to DAC Loop-Back Control
LOP
0
1
Loop-back Disable
Loop-back Enable
FMT (1,0)
Bit 3:2
Audio Data Format Select
These bits determine the input and output audio
data formats.
FMT1
FMT0
DAC
ADC
Data Format
Data Format
NAME
0
0
16-bit, MSB-first,
Right-justified
16-bit, MSB-first,
Left-justified
Format 0
0
1
20-bit, MSB-first,
Right-justified
20-bit, MSB-first,
Left-justified
Format 1
1
0
20-bit, MSB-first,
Left-justified
20-bit, MSB-first,
Left-justified
Format 2
1
1
20-bit, MSB-first,
I
2
S
20-bit, MSB-first,
I
2
S
Format 3
LRP:
Bit 1
ADC and DAC Polarity of LR-clock
Selection. Applies only to Formats
0 through 2.
LRP
0
1
Left-channel is “H”, Right-channel is “L”.
Left-channel is “L”, Right-channel is “H”.
FIGURE 12. Typical Connection Diagram for PCM3002/3003.
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
+
4.7μF
(2)
4.7μF
(2)
+
+
+
+
1μF
1μF
Control
Interface
Audio
Interface
+3V Analog V
CC
Rch In
Lch In
SYSCLK
L/R CLK
BIT CLK
DATA OUT
DATA IN
0.1μF
and
10μF
(1)
0.1μF and 10μF
(1)
0.1μF
and 10μF
(1)
4.7μF
(4)
+
4.7μF
(4)
+
Rch Out
Lch Out
MC
(6)
/DEM0
(7)
MD
(6)
/DEM1
(7)
RST
(6)
/PDAD
(7)
ML
(6)
/PDDA
(7)
ZFLG
(6)
/20BIT
(7)
+
4.7μF
(4)
+
R
PCM3002/3003
V
CC
1
V
CC
1
V
IN
R
V
REF
L
V
REF
R
V
IN
L
RST/PDAD
ML/PDDA
SYSCLK
LRCIN
BCKIN
DOUT
V
CC
2
AGND1
AGND2
V
COM
V
OUT
R
V
OUT
L
MC/DEM0
MD/DEM1
ZFLG/20BIT
DIN
V
DD
DGND
NOTES: (1) 0.1μF ceramic and 10μF tantalum, typical, depending on power supply quality and
pattern layout. (2) 4.7μF typical, gives settling time with 30ms (4.7μF x 6.4k
) time constant in
Power ON and Power-Down OFF period. (3) 1μF typical, gives 5.3Hz cut-off frequency of input
HPF in normal operation and gives settling time with 30ms (1μF x 30k
) time constant in Power
ON and Power -Down OFF period. (4) 4.7μF typical, gives 3.4Hz cut-off frequency of output HPF
in normal operation and gives settling time with 47ms (4.7μF x 10k
) time constant in Power ON
and Power-Down OFF period. (5) Post low pass filter with R
IN
>10k
, depending on requirement
of system performance. (6) MC, MD, ML, ZFLG, RST and 10k
pull-up resistor are for the
PCM3002. (7) DEM0, DEM1, 20BIT, PDAD, PDDA are for the PCM3003.
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