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參數(shù)資料
| 型號： | PCM18XT0 |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 169/183頁 |
| 文件大?。?/td> | 0K |
| 描述： | MODULE PROC PIC18F4685 |
| 標準包裝： | 1 |
| 附件類型： | 處理器模塊 |
| 適用于相關產品： | ICE2000 |
| 產品目錄頁面： | 658 (CN2011-ZH PDF) |
| 配用： | ICE2000-ND - EMULATOR MPLAB-ICE 2000 POD |
| 相關產品： | DVA18XP400-ND - DEVICE ADAPTER 18F4220 PDIP 40LD DVA18XP280-ND - DEVICE ADAPTER 18F2220 PDIP 28LD DVA18PQ440-ND - DEVICE ADAPTER 18F4220 TQFP 44LD |
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PIC18F46J50 FAMILY
DS39931D-page 86
2011 Microchip Technology Inc.
FIGURE 6-7:
USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)
6.3.3
ACCESS BANK
While the use of the BSR with an embedded 8-bit
address allows users to address the entire range of
data memory, it also means that the user must always
ensure that the correct bank is selected. Otherwise,
data may be read from or written to the wrong location.
This can be disastrous if a GPR is the intended target
of an operation, but an SFR is written to instead.
Verifying and/or changing the BSR for each read or
write to data memory can become very inefficient.
To streamline access for the most commonly used data
memory locations, the data memory is configured with
an Access Bank, which allows users to access a
mapped block of memory without specifying a BSR.
The Access Bank consists of the first 96 bytes of
memory (00h-5Fh) in Bank 0 and the last 160 bytes of
memory (60h-FFh) in Bank 15. The lower half is known
as the Access RAM and is composed of GPRs. The
upper half is where the device’s SFRs are mapped.
These two areas are mapped contiguously in the
Access Bank and can be addressed in a linear fashion
by an 8-bit address (Figure 6-6).
The Access Bank is used by core PIC18 instructions
that include the Access RAM bit (the ‘a’ parameter in
the instruction). When ‘a’ is equal to ‘1’, the instruction
uses the BSR and the 8-bit address included in the
opcode for the data memory address. When ‘a’ is ‘0’,
however, the instruction is forced to use the Access
Bank address map; the current value of the BSR is
ignored entirely.
Using this “forced” addressing allows the instruction to
operate on a data address in a single cycle without
updating the BSR first. For 8-bit addresses of 60h and
above, this means that users can evaluate and operate
on SFRs more efficiently. The Access RAM below 60h
is a good place for data values that the user might need
to access rapidly, such as immediate computational
results or common program variables. Access RAM
also allows for faster and more code efficient context
saving and switching of variables.
The mapping of the Access Bank is slightly different
when the extended instruction set is enabled (XINST
Configuration bit = 1). This is discussed in more detail
.
6.3.4
GENERAL PURPOSE
REGISTER FILE
PIC18 devices may have banked memory in the GPR
area. This is data RAM, which is available for use by all
instructions. GPRs start at the bottom of Bank 0
(address 000h) and grow upward toward the bottom of
the SFR area. GPRs are not initialized by a POR and
are unchanged on all other Resets.
Note
1:
The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to
the registers of the Access Bank.
2:
The MOVFF instruction embeds the entire 12-bit address in the instruction.
Data Memory
Bank Select(2)
7
0
From Opcode(2)
000
0
000h
100h
200h
300h
F00h
E00h
FFFh
Bank 0
Bank 1
Bank 2
Bank 14
Bank 15
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
Bank 3
through
Bank 13
00
1
0
1
111
7
0
BSR(1)
1
111
1
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