參數(shù)資料
型號: PCM18XT0
廠商: Microchip Technology
文件頁數(shù): 133/183頁
文件大小: 0K
描述: MODULE PROC PIC18F4685
標準包裝: 1
附件類型: 處理器模塊
適用于相關產(chǎn)品: ICE2000
產(chǎn)品目錄頁面: 658 (CN2011-ZH PDF)
配用: ICE2000-ND - EMULATOR MPLAB-ICE 2000 POD
相關產(chǎn)品: DVA18XP400-ND - DEVICE ADAPTER 18F4220 PDIP 40LD
DVA18XP280-ND - DEVICE ADAPTER 18F2220 PDIP 28LD
DVA18PQ440-ND - DEVICE ADAPTER 18F4220 TQFP 44LD
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2011 Microchip Technology Inc.
DS39931D-page 53
PIC18F46J50 FAMILY
FIGURE 4-8:
TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
4.4.3
RC_IDLE MODE
In RC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the internal
oscillator block. This mode allows for controllable
power conservation during Idle periods.
From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device is in another Run mode, first set IDLEN, then
clear the SCS bits and execute SLEEP. When the clock
source is switched to the INTOSC block, the primary
oscillator is shutdown and the OSTS bit is cleared.
When a wake event occurs, the peripherals continue to
be clocked from the internal oscillator block. After a wake
event, the CPU begins executing code being clocked by
the INTRC. The IDLEN and SCS bits are not affected by
the wake-up. The INTRC source will continue to run if
either the WDT or the FSCM is enabled.
4.5
Exiting Idle and Sleep Modes
An exit from Sleep mode, or any of the Idle modes, is
triggered by an interrupt, a Reset or a WDT time-out.
This section discusses the triggers that cause exits
from power-managed modes. The clocking subsystem
actions are discussed in each of the power-managed
modes sections (see Section 4.2 “Run Modes”,
).
4.5.1
EXIT BY INTERRUPT
Any of the available interrupt sources can cause the
device to exit from an Idle mode, or the Sleep mode, to
a Run mode. To enable this functionality, an interrupt
source must be enabled by setting its enable bit in one
of the INTCON or PIE registers. The exit sequence is
initiated when the corresponding interrupt flag bit is set.
On all exits from Idle or Sleep modes by interrupt, code
execution branches to the interrupt vector if the
GIE/GIEH bit (INTCON<7>) is set. Otherwise, code
execution continues or resumes without branching
4.5.2
EXIT BY WDT TIME-OUT
A WDT time-out will cause different actions depending
on which power-managed mode the device is, when
the time-out occurs.
If the device is not executing code (all Idle modes and
Sleep mode), the time-out will result in an exit from the
power-managed
mode
(see
and Section 4.3 “Sleep Mode”). If the device
is executing code (all Run modes), the time-out will
result in a WDT Reset (see Section 27.2 “Watchdog
).
The WDT and postscaler are cleared by one of the
following events:
Executing a SLEEP or CLRWDT instruction
The loss of a currently selected clock source (if
the FSCM is enabled)
4.5.3
EXIT BY RESET
Exiting an Idle or Sleep mode by Reset automatically
forces the device to run from the INTRC.
OSC1
Peripheral
Program
PC
CPU Clock
Q1
Q3
Q4
Clock
Counter
Q2
Wake Event
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