參數(shù)資料
型號(hào): PCM1738E2K
英文描述: 24-Bit, 192kHz Sampling, Advanced Segment, Audio-Stereo DIGITAL-TO-ANALOG CONVERTER
中文描述: 24位192kHz采樣,高級(jí)分段,音頻立體聲數(shù)字模擬轉(zhuǎn)換器
文件頁(yè)數(shù): 29/33頁(yè)
文件大小: 2274K
代理商: PCM1738E2K
PCM1738
SBAS174B
29
FIGURE 13. Architecture of Advanced Segment DAC.
+
Advanced
DWA
Analog
Output
ICOB
Decoder
3rd-Order,
5th-Level,
Current
Segment
DAC
0 62
Level
0 66
0 4
Level
Upper
6 Bits
MSB and
Lower 18 Bits
Digital
Input
24-Bit
8f
S
The PCM1738 utilizes the newly developed Advanced Seg-
ment DAC architecture to achieve excellent dynamic perfor-
mance and improved tolerance to clock jitter. The PCM1738
provides balanced current outputs, allowing the user to
optimize analog performance externally. The structure of the
Advanced Segment DAC architecture is shown in Figure 13.
Digital input data from the digital interpolation filter is split
into six upper bits and 18 lower bits. The upper six bits are
converted to ICOB (Inverted Complementary Offset Binary)
code. The lower 18 bits associated with the MSB are
processed by fifth-level, third-order, delta-sigma modulators
operated at 64f
S
by default conditions. The first level of the
modulator is equivalent to 1LSB of the above code con-
verter. The data groups processed in the ICOB converter and
the third-order delta-sigma modulator are summed together
to create up to 67 levels of digital code that is then processed
by the DWA (Data Weighted Averaging) to reduce noise
produced by element mismatch. The output data from the
DWA block is then converted to an analog output using a
differential current segment DAC.
To learn more details regarding the Advanced Segment
DAC architecture, please refer to the paper presented at the
109
th
AES Convention entitled “A 117db, D-Range, Cur-
rent-mode, Multi-Bit, Audio DAC for PCM and DSD Audio
Playback” by Nakao, Terasawa, Aoyagi, Terada, and
Hamasaki of Burr-Brown Japan (now part of Texas Instru-
ments).
THEORY OF OPERATION
ADVANCED SEGMENT DAC
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