參數(shù)資料
型號(hào): PCM1738E2K
英文描述: 24-Bit, 192kHz Sampling, Advanced Segment, Audio-Stereo DIGITAL-TO-ANALOG CONVERTER
中文描述: 24位192kHz采樣,高級(jí)分段,音頻立體聲數(shù)字模擬轉(zhuǎn)換器
文件頁(yè)數(shù): 24/33頁(yè)
文件大?。?/td> 2274K
代理商: PCM1738E2K
PCM1738
SBAS174B
24
FIGURE 10. Connection Diagram for External Digital Filter (Internal DF Bypass Mode) Application.
APPLICATION FOR EXTERNAL DIGITAL FILTER INTERFACE
APPLICATIONS FOR INTERFACING WITH THE
EXTERNAL DIGITAL FILTER PART
For some applications, it may be desirable to use an external
digital filter to perform the interpolation function, as it may
provide improved stopband attenuation or other special fea-
tures not available with the PCM1738’s internal digital filter.
The PCM1738 supports the use of an external digital filter,
including:
The DF1704 and DF1706 from Texas Instruments.
Pacific Microsonics PMD100/200 HDCD Filter/Decoder ICs.
Programmable Digital Signal Processors.
The external digital-filter application mode is available by
programming the following bits in the corresponding control
registers:
DFTH = 1 (Register 20)
DME = 0 (Register 18)
The pins used to provide the serial interface for the external
digital filter are shown in the application diagram of Figure 10.
The Word (WDCK) and Bit (BCK) clock signals, as well as
the audio data inputs (DATAL and DATAR) must be operated
at 8x or 4x the original sampling frequency at the input of the
digital filter.
SYSTEM CLOCK (SCKI) AND INTERFACE TIMING
The PCM1738, in external digital filter application, allows
any system-clock frequency synchronized with BCK and
WDCK. The system clock may be phase free with BCK and
WDCK. See Figure 17 for interface timing among WDCK,
BCK, DATAL, and DATAR.
AUDIO FORMAT
In external Digital-Filter Interface mode, the PCM1738
supports a right-justified audio format interface including
16-, 20-, and 24-bit audio data (see Figure 16) that should be
selected by FMT[2:0] of Control Register 18.
RST
ZEROL
ZEROR
WDCK
DATAL
BCK
SCKI
DGND
V
DD
SCKO
MDO
MDI
MC
CS
V
CC
3
AGND2
I
OUT
L–
I
OUT
L+
V
CC
2
V
CC
1
V
COM
3
I
REF
V
COM
2
V
COM
1
AGND1
I
OUT
R+
I
OUT
R–
DATAR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
WDCK (Word Clock)
DATA-L
BCK
SCK
DATA-R
Mode
Control
DF1704
DF1706
PMD200
Analog
Output Stage
Same as Standard
Application
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