參數(shù)資料
型號(hào): PCM1738E2K
英文描述: 24-Bit, 192kHz Sampling, Advanced Segment, Audio-Stereo DIGITAL-TO-ANALOG CONVERTER
中文描述: 24位192kHz采樣,高級(jí)分段,音頻立體聲數(shù)字模擬轉(zhuǎn)換器
文件頁(yè)數(shù): 27/33頁(yè)
文件大小: 2274K
代理商: PCM1738E2K
PCM1738
SBAS174B
27
DSD MODE CONFIGURATION AND FUNCTION CONTROLS
Configuration for DSD Interface mode:
DFTH = 1 (Register 20)
DME = 1 (Register 18)
Table V shows the register mapping available in DSD Mode.
TABLE V. Register Mapping in DSD Mode.
REGISTER
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
16
17
18
19
20
21
W/R
W/R
W/R
W/R
W/R
R
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
DMF1
CLKD
RSV
RSV
DMF0
CLKE
RSV
RSV
DME
(1)
OS1
OPE
DFTH
(1)
RSV
RSV
RSV
SRST
RSV
MRST
RSV
OS0
NOTE: (1) This bit is required for selection of the external Digital Filter mode. (2) “–” = function disabled.
DMF[1:0]
Analog FIR Performance Selection
These bits are available for Read/Write.
Default Value: 00
DMF[1:0]
00
01
10
11
Analog FIR Performance Select
DSD Filter 1
DSD Filter 2
DSD Filter 3
DSD Filter 4
Plots for the four Analog FIR filter responses are shown in the Typical Performance Curves of this data sheet.
OS[1:0]
Analog FIR Operation Speed Select Selection
These bits are available for Read/Write.
Default Value: 00
OS[1:0]
00
01
10
11
Operation Speed Select
f
SCKI
(default)
Reserved
Reserved
f
SCKI
/2
The OS bit in the DSD mode is used to select the operating rate of analog FIR.
REQUIREMENTS FOR SYSTEM CLOCK
The bit clock (BCK) for DSD Mode is required at pin 7 of the PCM1738. The frequency of the bit clock may be N times of
the sampling frequency. Generally, N is 64 in DSD application.
The interface timing between the bit clock, DATAL, and DATAR is required to meet the same setup and hold time
specifications as shown for the PCM Audio format interface in Figure 5.
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PCM1738E 24-Bit, 192kHz Sampling, Advanced Segment, Audio-Stereo DIGITAL-TO-ANALOG CONVERTER
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