參數(shù)資料
型號(hào): PCM1738E2K
英文描述: 24-Bit, 192kHz Sampling, Advanced Segment, Audio-Stereo DIGITAL-TO-ANALOG CONVERTER
中文描述: 24位192kHz采樣,高級(jí)分段,音頻立體聲數(shù)字模擬轉(zhuǎn)換器
文件頁(yè)數(shù): 15/33頁(yè)
文件大?。?/td> 2274K
代理商: PCM1738E2K
PCM1738
SBAS174B
15
FUNCTIONAL DESCRIPTIONS
ZERO DETECT
When the PCM1738 detects that the audio input data in the
L-channel or R-channel is continuously zero for 1024f
S
, the
PCM1738 sets ZEROL (pin 2) or ZEROR (pin 3) to HIGH.
Setting the INZD bit of mode register 19 can set both analog
outputs to the bipolar zero level when the input data of both
channels are zero.
SOFT MUTE
The PCM1738 supports mute operation by both hardware
and software control. When MUTE (pin 15) is set to HIGH,
both analog outputs are turned to the bipolar zero level.
When the MUTE bit in mode register 18 is set to “1”, both
analog outputs are also turned to the bipolar zero level. The
speed to turn to the bipolar zero level is set by the ATS0 and
ATS1 bits in mode register 19.
SERIAL CONTROL INTERFACE
The serial control interface is a 4-wire synchronous serial
port that operates asynchronously to the serial audio inter-
face and the system clock (SCKI). The serial control inter-
face is utilized to program the on-chip mode registers. The
control interface includes MDO (pin 11), MDI (pin 12), MC
(pin 13), and CS (pin 14). MDO is the serial data output,
used to read back the values of the mode registers; MDI is
the serial data input, used to program the mode registers;
MC is the serial bit clock, used to shift data in and out of the
control port; and CS is the mode control enable, used to
enable the internal mode register access. Figures 6 and 7
show the format and timing for the serial control interface.
SYMBOL
PARAMETER
MIN
MAX
UNITS
t
MCY
t
MCL
t
MCH
t
MHH
t
MLS
t
MLH
t
MDH
t
MDS
t
MOS
MC Pulse Cycle Time
MC Low Level Time
MC High Level Time
CS High Level Time
CS Falling Edge to MC Rising Edge
CS Hold Time
(1)
MDI Hold Time
MDI Set-Up Time
MC Falling Edge to MDO Stable
100
40
40
80
15
15
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
FIGURE 7. Control Interface Timing.
NOTE: (1) MC rising edge for LSB to CS rising edge.
50% of V
DD
50% of V
DD
50% of V
DD
ML
MC
MD
t
MLS
t
MCH
t
MCY
t
MDS
t
MDH
t
MCL
t
MHH
t
MLH
LSB
t
MOS
相關(guān)PDF資料
PDF描述
PCM1738E 24-Bit, 192kHz Sampling, Advanced Segment, Audio-Stereo DIGITAL-TO-ANALOG CONVERTER
PCM1739 24-Bit, 192kHz Sampling, Enhanced Multi-Level, Delta-Sigma, Audio DIGITAL-TO-ANALOG CONVERTER
PCM1739E 24-Bit, 192kHz Sampling, Enhanced Multi-Level, Delta-Sigma, Audio DIGITAL-TO-ANALOG CONVERTER
PCM1740 CONN,CPRSN,2-WAY
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