參數(shù)資料
型號: PCM1719E
英文描述: Stereo Audio DIGITAL-TO-ANALOG CONVERTER
中文描述: 立體聲音頻數(shù)字模擬轉(zhuǎn)換器
文件頁數(shù): 8/15頁
文件大?。?/td> 218K
代理商: PCM1719E
8
PCM1719
14
15
16
1
2
3
14
15
1/f
S
, f
S
= 32, 44.1, 48kHz
L_ch
R_ch
MSB
LSB
16
LRCIN (pin 4)
BCKIN (pin 6)
AUDIO DATA WORD = 16-BIT
DIN (pin 5)
1
2
3
14
15
MSB
LSB
16
16
17
18
1
2
3
16
17
MSB
LSB
18
AUDIO DATA WORD = 18-BIT
1
2
3
16
17
MSB
LSB
18
FIGURE 2. Data Input Timing of Normal Format ( MSB-first, right-justified); Lch = “H”, Rch = “L”.
FIGURE 3. Data Input Timing of I
2
S Data Format (Philips format); Lch = “L”, Rch = “H”.
PCM AUDIO INTERFACE
PCM audio data of the PCM1719 is accepted via LRCIN
(pin 4), DIN (pin 5) and BCKIN (pin 6). The PCM1719E
accepts both normal and I
2
S data input formats. The normal
data format is MSB-first, Two’s Complement and right-
justified. The I
2
S format is compatible with Philips’ serial
data protocol. In these formats, the serial data is 16- or 18-
bit input selectable. Figures 2 and 3 illustrate the input audio
data timing and format.
OPERATIONAL CONTROL
The Software Mode uses a three-wire interface on pins 24,
25 and 26. Pin 25 (MC) is used to clock in the serial control
data, pin 26 (ML) is used to latch the serial control data, and
pin 24 (MD) is used to load in the serial control register.
There are four distinct registers, with bits 9 and 10 (of 16)
determining which register is in use.
1
2
3
14
15
1/f
S
, f
S
= 32, 44.1, 48kHz
L_ch
R_ch
MSB
LSB
16
LRCIN (pin 4)
BCKIN (pin 6)
AUDIO DATA WORD = 16-BIT
DIN (pin 5)
1
2
3
14
15
MSB
LSB
16
1
2
3
16
17
MSB
LSB
18
AUDIO DATA WORD = 18-BIT
DIN (pin 5)
1
2
3
16
17
MSB
LSB
18
2
1
2
1
REGISTER CONTROL (Bits 9, 10)
REGISTER
B9 (A0)
B10 (A1)
0
1
2
3
0
1
0
1
0
0
1
1
Control data timing is shown in Figure 7. ML is used to latch
the data from the control registers. After each register’s
contents are checked in, ML should be taken “LOW” to
latch in the data. A “res” in the register indicates that
location is reserved for factory use. When loading the
registers, the “res” bits should be set “LOW”.
REGISTER 0
B15 B14 B13 B12 B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
res
res res res
res A1 A0 LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0
Register 0 is used to control left channel attenuation. Bits
0-7 (AL0-AL7) are used to determine the attenuation level.
The level of attenuation is given by:
ATT = [20log
10
(ATT_DATA/255)] dB
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