參數(shù)資料
型號(hào)： PCM1719E
英文描述： Stereo Audio DIGITAL-TO-ANALOG CONVERTER
中文描述： 立體聲音頻數(shù)字模擬轉(zhuǎn)換器
文件頁(yè)數(shù)： 10/15頁(yè)
文件大小： 218K
代理商： PCM1719E
10
PCM1719
Bit 2 is used to select the input word length. When bit 2 is
LOW, the input word length is set for 16 bits; when bit 2 is
HIGH, the input word length is set for 18 bits.
Bit 3 is used as an attenuation control. When bit 3 is set
HIGH, the attenuation data on Register 0 is used for both
channels, and the data in Register 1 is ignored. When bit 3
is LOW, each channel has separate attenuation data.
Bits 4 through 7 are used to determine the output format, as
shown in Table V:
PL0
PL1
PL2
PL3
Lch OUTPUT
Rch OUTPUT
NOTE
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
MUTE
MUTE
MUTE
MUTE
R
R
R
R
L
L
L
L
(L + R)/2
(L + R)/2
(L + R)/2
(L + R)/2
MUTE
R
L
(L + R)/2
MUTE
R
L
(L + R)/2
MUTE
R
L
(L + R)/2
MUTE
R
L
(L + R)/2
MUTE
REVERSE
STEREO
MONO
TABLE V. PCM1719 Output Mode Control.
Bit 1 is used to select the polarity of LRCIN (sample rate
clock). When bit 1 is LOW, a HIGH state on LRCIN is used
for the left channel, and a LOW state on LRCIN is used for
the right channel. When bit 1 is HIGH the polarity of LRCIN
is reversed.
FIGURE 4. Data Input Timing.
BCKIN Pulsewidth (High Level)
BCKIN Pulsewidth (Low Level)
BCKIN Pulse Cycle Time
BCKIN Rising Edge
¨
LRCIN Edge
LRCIN Edge
¨
BCKIN Rising Edge
DIN Setup Time
DIN Hold Time
t
BCH
t
BCL
t
BCY
BL
t
LB
t
DS
t
DH
50ns (min)
50ns (min)
100ns (min)
30ns (min)
30ns (min)
30ns (min)
30ns (min)
t
BCH
t
BCL
t
LB
t
BCY
t
BL
t
DH
t
DS
50% of V
DD
50% of V
DD
50% of V
DD
LRCIN
BCKIN
DIN
t
MCH
t
MCL
t
MCY
t
MLS
t
MDH
t
MDS
t
MLH
t
MLL
50% of V
DD
50% of V
DD
50% of V
DD
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6
B5 B4
B3 B2 B1 B0
ML (pin 18)
MC (pin 17)
MD (pin 16)
ML
MC
MD
MC Pulse Cycle
MC Pulsewidth “L”
MC Pulse Cycle “H”
MD Setup Time
MD Hold Time
ML Setup Time
ML Hold Time
ML Pulsewidth “L”
t
MCY
t
MCL
t
MCH
t
MDS
t
MDH
t
MLS
t
MLH
t
MLL
100ns (min)
50ns (min)
50ns (min)
30ns (min)
30ns (min)
30ns (min)
30ns (min)
30ns + 1SYSCLK (min)
FIGURE 5. Control Data Timing in Software Mode Control.
FIGURE 6. External Reset Timing.
t
RST
RSTB
50% of V
DD
RSTB Pulsewidth
20ns (min)
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