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參數(shù)資料
| 型號(hào)： | PCM1719E |
| 英文描述： | Stereo Audio DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 立體聲音頻數(shù)字模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 14/15頁 |
| 文件大?。?/td> | 218K |
| 代理商： | PCM1719E |
14
PCM1719
PGA
Digital
Lch
Rch
DEM-
PCM1719
CD
Player
DAI
External
LPF
THD
Meter
0dB/60dB
30KHz LPF on
Through
For test of S/N ratio and Dynamic Range, A-filter ON.
Test Disk
Shibasoku #725
FIGURE 14. Test Block Diagram.
TEST CONDITIONS
Figure 14 illustrates the actual test conditions applied to
PCM1719 in production. The external filter is necessary in
the production environment for the removal of noise result-
ing from the relatively long physical distance between the
unit and the test analyzer. In most actual applications, the
3rd-order filter shown in Figure 13 is adequate. Under
normal conditions, THD+N typical performance is –70dB
with a 30kHz low pass filter (shown here on the THD
meter), improving to –89dB when the external 20kHz 11th-
order filter is used.
JITTER SENSITIVITY
Delta-sigma DACs are by nature very sensitive to jitter on the
master clock. Phase noise on the clock will result in an
increase in noise, ultimately degrading dynamic range. It is
difficult to quantify the effect of jitter due to problems in
synthesizing low levels of jitter. One of the reasons delta-
sigma DACs are prone to jitter sensitivity is the large quanti-
zation noise when the modulator can only achieve two dis-
crete output levels (0 or 1). The multi-level delta-sigma DAC
has improved theoretical SNR because of multiple output
states. This reduces sensitivity to jitter. Figure 15 contrasts
jitter sensitivity between a one-bit PWM type DAC and multi-
level delta-sigma DAC. The data was derived using a simula-
tor, where clock jitter could be completely synthesized.
FIGURE 15. Simulation Results of Clock Jitter Sensitivity.
0
100
200
300
400
500
600
110
105
100
95
90
85
80
75
70
65
60
D
Clock Jitter (ps)
Multi-level
PWM
2
1
0
–1
2
48fs
14.4ps
FIGURE 16. Simulation Method for Clock Jitter.
HEADPHONE AMPLIFIER
PCM1719 has an integrated headphone amplifier which can
directly drive a 32
load, such as headphones. The amplifier
is configured in a gain of –2.8dB (inverting), and the
maximum output current is 12.5mA (rms). The maximum
output voltage is 0.8Vrms into a 64
load (stereo 32
headphones), based on the typical DAC full scale voltage
output of 3.1V (p-p). P
IN
L and P
IN
R should be AC-coupled
such that the input impedance for the headphone amplifier is
55k
typical, and the noninverting input is biased to V
CC
/2.
The headphone amplifier has no internal current limiting
circuit. It is recommended to used an external current limit-
ing resistor to avoid damage caused by overloading the
output, and avoid shorting P
OUT
L and P
OUT
R to ground. The
minimum output load of 64
includes any current limiting
resistor. If the input impedance of the headphone is 32
, a
current limiting resistor of 32
should be used. Figure 17
FIGURE 17. THD+N vs Input Signal, Output Load.
Input Signal (dB)
T
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–60
–50
–40
–30
–20
–10
0
10
V
: 5V
DAC Input: BPZ
V
= 3.1Vp-p (0dB)
f = 1kHz
20kHz Bandwidth Limitation
R
P
= 32
R
L
= 40
48
64
RP
RL = RP + RH
RH
Headphone
Resistor
Test
Point
P
OUT
Current Limit
Resistor
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