
User's Note for PCLD-818L Revision A2 Card
The purpose of this 'User's Note' is to inform you of the new jumper
settings on the PCL-818L revised A2 card. If your PCL-818L card is
revision A1, this note will not apply to you.
The revision change is to simplify the multiplexing capability of the
PCL-818L. With the new jumpers onboard, JP8, JP9, JP10 and JP11,
you can select which cable controls the daughter boards connected.
This is done via either the D-type 37-pin connector or the original
20-pin connector. These cables, CN1 and CN3, use digital control
signal outputs D0 to D3. Please contact your distributor to find out
exactly which daughter boards can support this special feature.
To connect daughter boards without this function, set the jumpers to
the 'D' side (left hand side). With this configuration the digital
signals D0 to D3 will be on the 20-pin connector CN1. This is the
standard setup for the PCL-818L revision A1.
The default jumper setting on the PCL-818L revision A2 is with the
jumpers set to the 'S' (right hand side). In this configuration, the
digital output signals D0 to D3 will be on the 37-pin connector CN3.
The signal pins on CN1 will now be floating.
JP8 to JP11
D0
D1
D2
D3
S0
S1
S2
S3
JP8 to JP11
Digital Output
to CN3 (37-pin)
Digital Output
to CN1 (20-pin)
Default
D0
D1
D2
D3
S0
S1
S2
S3
Connector CN3
Pin Assignments
Connector
CN1 Pin
Assignments
Jumper
Configuration
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
D/O 0
D/O 2
D/O 4
D/O 6
D/O 8
D/O 10
D/O 12
D/O 14
D.GND
+5 V
D/O 1
D/O 3
D/O 5
D/O 7
D/O 9
D/O 11
D/O 13
D/O 15
D.GND
+12 V
2
1
4
5
6
7
8
9
10
11
12
13
15
16
14
17
18
19
20
21
3
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
A/DH 0
A/DH 1
A/DH 2
A/DH 3
A/DH 4
A/DH 5
A/DH 6
A/DH 7
A.GND
A.GND
VREF
S0
+12 V
S2
D.GND
NC
COUNTER 0 CLK
COUNTER 0 OUT
+5 V
A/DL 0
A/DL 1
A/DL 2
A/DL 3
A/DL 4
A/DL 5
A/DL 6
A/DL 7
A.GND
A.GND
DA 0 OUT
DA 0V REFIN
S1
S3
DGND
TRIG0
COUNTER 0 GATE
PACER