參數(shù)資料
型號： PCK2057
廠商： NXP Semiconductors N.V.
英文描述： H TYPE TAP
中文描述： 70 - 190兆赫的I2C差分時鐘驅(qū)動器1:10
文件頁數(shù)： 7/12頁
文件大?。?/td> 95K
代理商： PCK2057
Philips Semiconductors
Product data
PCK2057
70 – 190 MHz I
2
C differential 1:10 clock driver
2001 Jun 12
7
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions.
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNIT
MIN
—
TYP
1
—
—
—
—
—
—
V
DDQ
/2
—
—
150
3
205
4
MAX
–1.2
—
—
0.1
0.6
0.4
V
IK
Input voltage
All inputs
V
DDQ
= 2.3 V; I
I
= –18 mA
V
DDQ
= min to max; I
OH
= –1 mA
V
DDQ
= 2.3 V; I
OH
= –12 mA
V
DDQ
= min to max; I
OL
= 1 mA
V
DDQ
= 2.3 V; I
OL
= 12 mA
V
DD
I
2
C = 3.0 V; I
OL
= 3 mA
V
V
V
V
V
V
V
μ
A
μ
A
μ
A
μ
A
mA
mA
V
OH
HIGH level output voltage
HIGH-level output voltage
V
DDQ
– 0.1
1.7
—
—
—
V
DDQ
/2 – 0.2
—
—
—
—
—
—
LOW level output voltage
LOW-level output voltage
V
OL
SDA
V
OX
I
I
I
OZ
Output differential cross voltage
Input current
High impedance state output current
Power-down current on V
DDQ
+ AV
DD
Power-down current on V
DD
I
2
C
Dynamic current on V
DDQ
Supply current on AV
DD
V
DDQ
/2 + 0.2
±
10
±
10
250
20
230
6
CLK, FBIN
V
DDQ
= 2.7 V; V
I
= 0 V to 2.7 V
V
DDQ
= 2.7 V; V
O
= V
DDQ
or GND
CLK at 0 MHz;
Σ
of I
DD
and AI
DD
CLK at 0 MHz; V
DDQ
= 3.6 V
f
O
= 100 MHz
f
O
= 100 MHz
V
I
2
C = 3.6 V;
SCL and SDA = 3.6V
V
DDQ
= 2.5 V; V
I
= V
DDQ
or GND
I
DDPD
I
DD
AI
DD
I
DD
I
2
C
Supply current on V
DD
I
2
C
—
1
2
mA
C
I
Input capacitance
2
2.8
3
pF
NOTES:
1. All typical values are at respective nominal V
DDQ
.
TIMING REQUIREMENTS
Over recommended ranges of supply voltage and operating free-air temperature.
SYMBOL
PARAMETER
LIMITS
UNIT
MIN
70
40
—
MAX
190
60
100
f
CLK
Clock frequency
Input clock duty cycle
Stabilization time
1
MHz
%
μ
s
NOTE:
1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained,
a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation
delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input
modulation under SSC application.
TIMING REQUIREMENTS FOR THE I
2
C INTERFACE
Over recommended ranges of operating free-air temperature and V
DD
I
2
C from 3.3 V to 3.6 V..
SYMBOL
PARAMETER
STANDARD-MODE I
2
C-BUS
UNIT
MIN
—
4.7
4.7
4.0
4.7
4.0
—
—
250
0
4
MAX
100
—
—
—
—
—
1000
300
—
—
—
f
SCL
t
BUF
t
SU;STA
t
HD;STA
t
LOW
t
HIGH
t
r
t
f
t
SU;DAT
t
HD;DAT
t
SU;STO
SCL clock frequency
Bus free time between a STOP and START condition
Set-up time for a repeated START condition
Hold time (repeated) START condition. After this period, the first clock is generated.
LOW period of the SCL clock
HIGH period of the SCL clock
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
DATA set-up time
DATA hold time
Set-up time for STOP condition
kHz
μ
s
μ
s
μ
s
μ
s
μ
s
ns
ns
ns
ns
μ
s
相關(guān)PDF資料
PDF描述
PCK2057DGG 70 - 190 MHz I2C differential 1:10 clock driver
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PCK2057DGG,512 功能描述:鎖相環(huán) - PLL DN RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
PCK2057DGG,518 功能描述:鎖相環(huán) - PLL DN RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
PCK2057DGG-T 功能描述:鎖相環(huán) - PLL DN RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
PCK210 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Low voltage dual 1-5 differential ECL/PECL clock driver
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