參數資料
型號： PCK2057
廠商： NXP Semiconductors N.V.
英文描述： H TYPE TAP
中文描述： 70 - 190兆赫的I2C差分時鐘驅動器1:10
文件頁數： 2/12頁
文件大小： 95K
代理商： PCK2057
Philips Semiconductors
Product data
PCK2057
70 – 190 MHz I
2
C differential 1:10 clock driver
2
2001 Jun 12
853–2253 26485
FEATURES
Optimized for clock distribution in DDR (Double Data Rate)
SDRAM applications supporting DDR 200/266/300/333
Full DDR solution provided when used with PCK2002P or
PCK2002PL, and PCK2022RA
1-to-10 differential clock distribution
Very low jitter (
<
100 ps)
Operation from 2.2 V to 2.7 V AV
DD
and 2.3 V to 2.7 V V
DD
SSTL_2 interface clock inputs and outputs
HCSL to SSTL_2 input conversion
Test mode enables buffers while disabling PLL
Tolerant of Spread Spectrum input clock
3.3 V I
2
C support with 3.3 V V
DD
I
2
C
2.5 V I
2
C support with 2.5 V V
DD
I
2
C
Form, fit, and function compatible with CDCV850
DESCRIPTION
The PCK2057 is a high-performance, low-skew, low-jitter zero delay
buffer that distributes a differential clock input pair (CLK, CLK) to ten
differential pairs of clock outputs and one differential pair of
feedback clock outputs. The clock outputs are controlled by the
clock inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), the
2-line serial interface (SDA, SCL), and the analog power input
(AV
DD
). The two-line serial interface (I
2
C) can put the individual
output clock pairs in a high-impedance state. When AV
DD
is tied to
GND, the PLL is turned off and bypassed for test purposes.
The device provides a standard mode (100 kbits) I
2
C interface for
device control. The implementation is as a slave/receiver. The serial
inputs (SDA, SCL) provide integrated pull-up resistors (typically
100 k
).
Two 8-bit, 2-line serial registers provide individual enable control for
each output pair. All outputs default to enabled at power-up. Each
output pair can be placed in a high-impedance mode, when a
low-level control bit is written to the control register. The registers
must be accessed in sequential order (i.e., random access of the
registers is not supported). The I
2
C interface circuit can be supplied
with either 2.5 V or 3.3 V (V
DD
I
2
C).
Since the PCK2057 is based on PLL circuitry, it requires a
stabilization time to achieve phase-lock of the PLL. This stabilization
time is required following power-up.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
21
22
23
24
41
42
43
44
45
46
47
48
GND
Y
0
Y
0
V
DDQ
Y
1
Y
1
GND
Y
2
Y
2
GND
V
DDQ
SCL
CLK
CLK
V
DD
I
2
C
AV
DD
AGND
GND
Y
3
Y
3
V
DDQ
Y
4
Y
4
GND
GND
Y
5
Y
5
V
DDQ
Y
6
Y
6
GND
GND
Y
7
Y
7
V
DDQ
SDA
FBIN
FBIN
V
DDQ
FBOUT
FBOUT
GND
Y
8
Y
8
V
DDQ
Y
9
Y
9
GND
SW00506
PIN DESCRIPTION
PINS
SYMBOL
DESCRIPTION
1, 7, 8, 18, 24, 25, 31,
41, 42, 48
GND
Ground
2, 3, 5, 6, 9, 10, 19, 20,
22, 23, 26, 27, 29, 30,
32, 33, 39, 40, 43, 44,
46, 47
Y
, Y
,
FBOUT, FBOUT
Buffered output
copies of input clock,
CLK
4, 11, 21, 28, 34, 38,
45
V
DDQ
2.5 V supply
13, 14, 35, 36
CLK, CLK,
FBIN, FBIN
Differential clock
inputs and feedback
differential clock
inputs
16
AV
DD
AGND
Analog power
17
Analog ground
37
SDA
Serial data
12
SCL
V
DD
I
2
C
Serial clock
I
2
C power
15
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
DRAWING NUMBER
48-Pin Plastic TSSOP
0 to +70
°
C
PCK2057DGG
SOT362-1
相關PDF資料
PDF描述
PCK2057DGG 70 - 190 MHz I2C differential 1:10 clock driver
PCK2509SLDH 50-150 MHz 1:9 SDRAM clock driver
PCK2509SA H TYPE TAP
PCK2509SADH H TYPE TAP
PCK2509SL H TYPE TAP
相關代理商/技術參數
參數描述
PCK2057DGG 功能描述:鎖相環(huán) - PLL DN RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
PCK2057DGG,512 功能描述:鎖相環(huán) - PLL DN RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
PCK2057DGG,518 功能描述:鎖相環(huán) - PLL DN RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
PCK2057DGG-T 功能描述:鎖相環(huán) - PLL DN RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
PCK210 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Low voltage dual 1-5 differential ECL/PECL clock driver
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