參數(shù)資料
型號(hào)： PCK2057
廠商： NXP Semiconductors N.V.
英文描述： H TYPE TAP
中文描述： 70 - 190兆赫的I2C差分時(shí)鐘驅(qū)動(dòng)器1:10
文件頁(yè)數(shù)： 6/12頁(yè)
文件大?。?/td> 95K
代理商： PCK2057
Philips Semiconductors
Product data
PCK2057
70 – 190 MHz I
2
C differential 1:10 clock driver
2001 Jun 12
6
ABSOLUTE MAXIMUM RATINGS (see Note 1)
Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNIT
MIN
0.5
0.5
–0.5
–0.5
–0.5
—
—
—
—
–65
MAX
3.6
4.6
V
DDQ
/AV
DD
V
DD
I
2
C
Supply voltage range
I
2
C supply voltage range
V
V
V
V
V
V
I
Input voltage range
except SCL and SDA
SCL and SDA
see Notes 2 and 3
see Notes 2 and 3
see Notes 2 and 3
V
I
< 0 or V
I
> V
DDQ
V
O
< 0 or V
O
> V
DDQ
V
O
= 0 to V
DDQ
V
DDQ
+ 0.5
V
DD
I
2
C + 0.5
V
DDQ
+ 0.5
±
50
±
50
±
50
±
100
+150
V
O
I
IK
I
OK
I
O
Output voltage range
Input clamp current
Output clamp current
Continuous output current
Continuous current to GND or V
DDQ
Storage temperature range
mA
mA
mA
mA
°
C
T
stg
NOTES:
1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions”
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. This value is limited to 3.6 V maximum.
RECOMMENDED OPERATING CONDITIONS (see Note 1)
SYMBOL
PARAMETER
TEST
LIMITS
UNIT
CONDITIONS
MIN
2.3
2.2
2.3
TYP
—
—
—
MAX
2.7
2.7
3.6
V
DDQ
AV
DD
V
DD
I
2
C
CLK, CLK,
HCSL buffer only
CLK, CLK
FBIN, FBIN
SDA, SCL
CLK, CLK,
HCSL buffer only
CLK, CLK
FBIN, FBIN
SDA, SCL
V
V
V
Supply voltage
see Note 2
—
0
0.24
V
V
IL
LOW-level input voltage
–0.3
—
—
—
—
—
V
DDQ
– 0.4
V
DDQ
/2 – 0.18
0.3
×
V
DD
I
2
C
V
V
V
0.66
0.71
—
V
V
IH
HIGH-level input voltage
0.4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
V
DDQ
+ 0.3
—
—
V
DDQ
+ 0.3
V
DDQ
+ 0.6
V
DDQ
+ 0.6
0.55
×
(V
IH
– V
IL
)
–12
12
3
4
33.3
–0.50
+70
V
V
V
V
V
V
V
V
DDQ
/2 + 0.18
0.7
×
V
DD
I
2
C
–0.3
0.36
0.2
0.45
×
(V
IH
– V
IL
)
—
—
—
1
30
0
0
DC input signal voltage
see Note 3
see Note 4
see Note 4
see Note 5
V
ID
Differential input sig
voltage
DC: CLK, FBIN
AC: CLK, FBIN
V
IX
I
OH
Input differential pair cross-voltage
HIGH-level output current
mA
mA
mA
V/ns
kHz
%
°
C
I
OL
LOW level output current
LOW-level output current
SDA
SR
Input slew rate
SSC modulation frequency
SSC clock input frequency deviation
Operating free-air temperature
see Figure 3
T
amb
NOTES:
1. Unused inputs must be held HIGH or LOW to prevent them from floating.
2. All devices on the I
2
C-bus, with input levels related to V
DD
I
2
C, must have one common supply line to which the pull-up resistor is connected.
3. DC input signal voltage specifies the allowable DC execution of differential input.
4. Differential input signal voltage specifies the differential voltage |V
TR
– V
CP
| required for switching, where V
TR
is the true input level, and V
CP
is the complementary input level.
5. Differential cross-point voltage is expected to track variations of V
DD
and is the voltage at which the differential signals must be crossing.
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