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參數(shù)資料
| 型號： | PCK2057 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | H TYPE TAP |
| 中文描述： | 70 - 190兆赫的I2C差分時(shí)鐘驅(qū)動(dòng)器1:10 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 95K |
| 代理商： | PCK2057 |
Philips Semiconductors
Product data
PCK2057
70 – 190 MHz I
2
C differential 1:10 clock driver
2001 Jun 12
5
SERIAL CONFIGURATION MAP
The serial bits will be read by the clock buffer in the following order:
Byte 0 – Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 – Bits 7, 6, 5, 4, 3, 2, 1, 0
All unused register bits (Reserved and “—”) should be designed as “Don’t Care”. It is expected that the controller will force all of these bits to a
“0” level.
All register bits labeled “Initialize to 0” must be written to zero during initialization. Failure to do so may result in a higher than normal operating
current.
Byte 0:
1 = enable; 0 = disable
BIT
7
6
5
4
3
2
1
0
NOTE:
1. Inactive means outputs are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be
configured during the normal modes of operation.
Active/inactive register
PIN#
2, 3
5, 6
9, 10
19, 20
22, 23
47, 46
44, 43
40, 39
NAME
CLK0, CLK0
CLK1, CLK1
CLK2, CLK2
CLK3, CLK3
CLK4, CLK4
CLK5, CLK5
CLK6, CLK6
CLK7, CLK7
INITIAL VALUE
1
1
1
1
1
1
1
1
DESCRIPTION
Enable/Disable Outputs
Enable/Disable Outputs
Enable/Disable Outputs
Enable/Disable Outputs
Enable/Disable Outputs
Enable/Disable Outputs
Enable/Disable Outputs
Enable/Disable Outputs
Byte 1:
1 = enable; 0 = disable
BIT
7
6
5
4
3
2
1
0
NOTE:
1. Inactive means outputs are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be
configured during the normal modes of operation.
Active/inactive register
PIN#
30, 29
27, 26
—
—
—
—
—
—
NAME
CLK8, CLK8
CLK9, CLK9
—
—
—
—
—
—
INITIAL VALUE
1
1
0
0
0
0
0
0
DESCRIPTION
Enable/Disable Outputs
Enable/Disable Outputs
Reserved
Reserved
Reserved
Reserved
Power-Down Mode Disable/Enable
HCSL Enable/Disable
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCK2057DGG | 功能描述:鎖相環(huán) - PLL DN RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PCK2057DGG,512 | 功能描述:鎖相環(huán) - PLL DN RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PCK2057DGG,518 | 功能描述:鎖相環(huán) - PLL DN RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PCK2057DGG-T | 功能描述:鎖相環(huán) - PLL DN RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PCK210 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Low voltage dual 1-5 differential ECL/PECL clock driver |
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