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參數(shù)資料
| 型號： | PCI-PIO |
| 英文描述： | KARTE E/A 48 KANAL PCI BUS |
| 中文描述： | KARTE E / A值48卡納爾PCI總線 |
| 文件頁數(shù)： | 20/24頁 |
| 文件大小： | 81K |
| 代理商： | PCI-PIO |
Page 14
Programming Details
Chapter 3
Page 14
01270187.doc
Blue Chip Technology Ltd.
To enable the generation of an interrupt or a combination of interrupts, an
enable word must be written to the Interrupt Enable Register at Base + C (Hex),
as shown below:-
Interrupt Enable Register (Base + C)
Bit no.
b7
b6
b5
b4
b3
b2
b1
b0
Function
Not used
Counter/timer 2 interrupt control
Counter/timer 1 interrupt control
Counter/timer 0 interrupt control
Port BC3 interrupt control
Port BC0 interrupt control
Port AC3 interrupt control
Port AC0 interrupt control
(1 = Enable, 0 = Disable)
(1 = Enable, 0 = Disable)
(1 = Enable, 0 = Disable)
(1 = Enable, 0 = Disable)
(1 = Enable, 0 = Disable)
(1 = Enable, 0 = Disable)
(1 = Enable, 0 = Disable)
When an interrupt is recognised by the processor, the source or sources of
interrupt may be read from the Interrupt Status Register at Base + D (Hex), as
shown below:-
Interrupt Status Register (Base + D)
Bit no.
b7
b6
b5
b4
b3
b2
b1
b0
Function
Not used
Counter/timer 2 interrupt occurred
Counter/timer 1 interrupt occurred
Counter/timer 0 interrupt occurred
Port BC3 interrupt control occurred
Port BC0 interrupt control occurred
Port AC3 interrupt control occurred
Port AC0 interrupt control occurred
Having serviced an interrupt, the source may be cleared by momentarily
clearing the relevant bit in the Interrupt Enable Register.
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