參數(shù)資料
型號(hào)： PCI-PIO
英文描述： KARTE E/A 48 KANAL PCI BUS
中文描述： KARTE E / A值48卡納爾PCI總線
文件頁(yè)數(shù)： 13/24頁(yè)
文件大?。?/td> 81K
代理商： PCI-PIO
Chapter 3
Programming Details
Page 7
Blue Chip Technology Ltd.
01270187.doc
Page 7
The 8254 contains three 16-bit Counter/timers each of which has separate clock
and enable inputs and an output, all of which are TTL compatible. Connections
to these signals should be kept as short as possible, less than 2 metres is
recommended.
The 8254 appears to the PC as four ports. The first three are count registers for
the three counter/timers, and the fourth is a Control Register which configures
the mode of operation of the three counters. These are accessed at the addresses
shown in the map below.
A summary of the codes required to change the port operations are given later.
Address Map
The address map for the PCI-PIO occupies a 16-byte block of addresses.
All the following addresses are relative to PCI base address register 2, located at
address 18 (hex) in the PCI configuration space.
ADDRESS
FUNCTION
READ/
WRITE
R/W
R/W
R/W
W
R/W
R/W
R/W
W
R/W
R/W
R/W
W
R/W
R
R/W
R/W
Base + 0
Base + 1
Base +2
Base + 3
Base + 4
Base + 5
Base + 6
Base + 7
Base + 8
Base + 9
Base + 10
Base + 11
Base + 12
Base + 13
Base + 14
Base + 15
PIO 1, Port A Input/Output Register (Channel 0 to 7)
PIO 1, Port B Input/Output Register (Channel 8 to 15)
PIO 1, Port C Input/Output Register (Channel 16 to 23)
PIO 1, Control Register
PIO 2, Port A Input/Output Register (Channel 24 to 31)
PIO 2, Port B Input/Output Register (Channel 32 to 39)
PIO 2, Port C Input/Output Register (Channel 40 to 47)
PIO 2, Control Register
Counter/timer 0 Count Register
Counter/timer 1 Count Register
Counter/timer 2 Count Register
Counter/timer Control Register
Interrupt enable register
Interrupt status register
Counter control register A
Counter control register B
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