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參數(shù)資料
| 型號： | PCI-PIO |
| 英文描述： | KARTE E/A 48 KANAL PCI BUS |
| 中文描述： | KARTE E / A值48卡納爾PCI總線 |
| 文件頁數(shù)： | 17/24頁 |
| 文件大?。?/td> | 81K |
| 代理商： | PCI-PIO |
Chapter 3
Programming Details
Page 11
Blue Chip Technology Ltd.
01270187.doc
Page 11
Counter Control
The control and output lines of the counter/timer may be accessed on the rear
panel connector by sacrificing some of the digital I/O lines.
The clock inputs of the i8254 counter/timer are selected using the Counter Input
Select Register A at Base + E (Hex), as shown below:-
Counter Input Select Register A (Base + E)
Bit no.
b7
Function
PBB0 = Counter 2 output
PBB1 = Counter 0 output
PBB2 = Counter 1 output
0 = Interrupt on counter out low
1 = Interrupt on counter out high
00 = 4 MHz oscillator
01 = PBB2 port line
10 = Counter 1 output
11 = PBC0 port line
00 = 4 MHz oscillator
01 = PBB1 port line
10 = Counter 0 output
11 = PAC3 port line
00 = 4 MHz oscillator
01 = PBB0 port line
10 = Counter 2 output
11 = PAC0 port line
Enable counter outputs such that
b6
Counter 0 interrupt level:-
b5..b4
Counter 2 clock source:-
b3..b2
Counter 1 clock source:-
b1..b0
Counter 0 clock source:-
If Bit b7 in the counter control register is set, then the counter outputs are
enabled onto port lines PBB0, PBB1 & PBB2, which connect to the 50 way
D-type connector. Consequently this port must be set as an input in the relevant
71055 device to avoid contention. This same condition applies to any port line
which is used for a counter/timer function.
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