參數(shù)資料
型號： PCI-DIO
英文描述： KARTE E/A 32 KANAL PCI BUS
中文描述： KARTE E / A值32卡納爾PCI總線
文件頁數(shù)： 16/21頁
文件大?。?/td> 83K
代理商： PCI-DIO
Chapter 3
Programming Details
Page 12
01270192.doc
To enable the generation of an interrupt or a combination of interrupts, an
enable word must be written to the Interrupt Enable Register at Base + 0 (Hex),
as shown below:-
Interrupt Enable Register (Base + 0)
Bit no.
b7
b6
b5
b4
b3
b2
b1
b0
Function
Not used
Not used
Not used
Counter/timer 2 interrupt control
Counter/timer 1 interrupt control
Counter/timer 0 interrupt control
Change of state 1 interrupt control
Change of state 0 interrupt control
(1 = Enable, 0 = Disable)
(1 = Enable, 0 = Disable)
(1 = Enable, 0 = Disable)
(1 = Enable, 0 = Disable)
(1 = Enable, 0 = Disable)
When an interrupt is recognised by the processor, the source or sources of
interrupt may be read from the Interrupt status register at Base + 1 (Hex), as
shown below:-
Interrupt Status Register (Base + 1)
Bit no.
b7
b6
b5
b4
b3
b2
b1
b0
Function
Not used
Not used
Not used
Counter/timer 2 interrupt occurred
Counter/timer 1 interrupt occurred
Counter/timer 0 interrupt occurred
Change of state 1 interrupt occurred
Change of state 0 interrupt occurred
Having serviced an interrupt, the source may be cleared by momentarily
clearing the relevant bit in the interrupt enable register.
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