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參數(shù)資料
| 型號： | PCI-DIO |
| 英文描述： | KARTE E/A 32 KANAL PCI BUS |
| 中文描述： | KARTE E / A值32卡納爾PCI總線 |
| 文件頁數(shù)： | 13/21頁 |
| 文件大?。?/td> | 83K |
| 代理商： | PCI-DIO |
Chapter 3
Programming Details
Page 9
01270192.doc
Counter Control
The control and output lines of the counter/timer may be accessed on the rear
panel connector by sacrificing some of the digital I/O lines.
The clock inputs of the i8254 counter/timer are selected using the Counter Input
Select Register A at Base + 2 (Hex), as shown below:-
Counter Input Select Register A (Base + 2)
Bit no.
b7
b6
Function
Not used
Counter 0 interrupt level:-
0 = Interrupt on counter out low
1 = Interrupt on counter out high
00 = 4 MHz clock
01 = IN5 input line
10 = Counter 1 output
11 = IN9 input line
00 = 4 MHz clock
01 = IN3 input line
10 = Counter 0 output
11 = IN9 input line
00 = 4 MHz clock
01 = IN1 input line
10 = Counter 2 output
11 = IN9 input line
b5..b4
Counter 2 clock source:-
b3..b2
Counter 1 clock source:-
b1..b0
Counter 0 clock source:-
The digital input bandwidth is limited such that the external clock inputs cannot
be guaranteed at frequencies in excess of 10kHz. Similarly, the external enable
inputs can only time external events to an accuracy of 100
μ
S.
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