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參數(shù)資料
| 型號(hào)： | PCI-ADC |
| 英文描述： | MULTIFUNKTIONSKARTE 44 KANAL PCI BUS |
| 中文描述： | MULTIFUNKTIONSKARTE 44卡納爾PCI總線 |
| 文件頁數(shù)： | 29/35頁 |
| 文件大?。?/td> | 124K |
| 代理商： | PCI-ADC |
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Chapter 3
Programming Details
Page 21
Blue Chip Technology Ltd.
01270193.doc
Page 21
Note:
Counter / Timer interrupts are generated on the falling edge of the
timer outputs. This may limit the modes in which the timers can be
operated as interrupt sources.
To enable an interrupt or a combination of interrupts to be generated, an enable
word must be written to the Interrupt Enable Register at Base 2 + 9
h
, as shown
below:-
Interrupt Enable Register
(Base 2 + 9
h
) Read/write
Function
1 = Enable, 0 = Disable
1 = Enable, 0 = Disable
1 = Enable, 0 = Disable
1 = Enable, 0 = Disable
1 = Enable, 0 = Disable
1 = Enable, 0 = Disable
1 = Enable, 0 = Disable
1 = Enable, 0 = Disable
Bit no.
b7
b6
b5
b4
b3
b2
b1
b0
INT7 control - FIFO Half Full
INT6 control - FIFO Not Empty
INT5 control - ADC Not Busy
INT4 control - Counter/timer 2 output
INT3 control - Counter/timer 1 output
INT2 control - Counter/timer 0 output
INT1 control - PC3 interrupt control
INT0 control - PC0 interrupt control
When an interrupt is recognised by the processor, the source or sources of
interrupt may be determined by reading the Interrupt status register at
Base 2 + 0A
h
, as shown below:-
Interrupt Status Register
(Base 2 + 0A
h
) Read only
Function
Bit no.
b7
b6
b5
b4
b3
b2
b1
b0
INT7 status - FIFO Half Full
INT6 status - FIFO Not Empty
INT5 status - ADC Not Busy
INT4 status - Counter/timer 2 output
INT3 status - Counter/timer 1 output
INT2 status - Counter/timer 0 output
INT1 status - PC3 interrupt status
INT0 status - PC0 interrupt status
Having serviced an interrupt, the source should be cleared by momentarily
clearing the relevant bit in the interrupt enable register.
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| PCI-C6600S4-2-67-167 | 制造商:Johnson Components 功能描述:SBC;DSP, 2 C9701, 2MB SRAM, IN |
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