
Chapter 3
Programming Details
Page 7
Blue Chip Technology Ltd.
01270193.doc
Page 7
If this FIFO memory is not required, it may be ignored, as its actions are
transparent to the user. For example, if a single channel is to be converted, then
the conversion is initiated and when complete, indicated by either the ‘busy’
flag being negated, the ‘FIFO empty’ flag being negated, or from interrupts, the
sample may then be read directly from the analogue input sample port.
If, however, a series of samples are required before any processing begins, or the
software overhead of reading the card is so great that it must be performed
infrequently, then the FIFO may be used to store the samples as they are taken,
with processor intervention only being required when the FIFO is full. The
samples may then be read.
Conversion may be initiated under software control, or by a hardware trigger
which may be generated either from counter/ timer 0, 1, or 2, or from an
external trigger input.
The ADC busy and FIFO flags are accessible in the Analogue Input Status
Register (see below).
Conversion Control
Conversion may be of a single channel, or of a number of channels, scanned
sequentially. It may be initiated under software control or by a hardware trigger
from a number of sources. Single channel conversion is normally initiated
under software control. Conversion of a number of channels would normally be
under hardware control, although software control is feasible.
Two registers control the ADC section: the Input Select Register and the
Conversion Control Register. Both have a number of functions. The Input
Select Register controls the input channel, the gain, and the selection of single,
differential or calibration inputs. The Conversion Control Register selects the
conversion trigger source, whether a single or multiple channels are to be
converted, and whether conversion is single or continuous.
Interrupts may be generated on the following conditions (see Interrupt Status
Register):-
ADC not busy (i.e. conversion complete)
FIFO half full
FIFO not empty