參數(shù)資料
型號: PCI-ADC
英文描述: MULTIFUNKTIONSKARTE 44 KANAL PCI BUS
中文描述: MULTIFUNKTIONSKARTE 44卡納爾PCI總線
文件頁數(shù): 26/35頁
文件大小: 124K
代理商: PCI-ADC
Page 18
Programming Details
Chapter 3
Page 18
01270193.doc
Blue Chip Technology Ltd.
Mode 0
When programmed, the output pin will go LOW. When the counter decrements
from the value loaded into the count registers to zero, the output pin will go
HIGH. It will remain high until the count is re-programmed into the count
registers.
Mode 1
When the count registers are programmed the output pin will be HIGH. When
a LOW going signal is applied to the gate input, the count starts and the output
will fall LOW, returning HIGH at the end of the count. The gate lines are
permanently enabled on the PCI-ADC.
Mode 2
This mode operates as a frequency divider. When programmed the output pin is
HIGH. When the count decrements to a value of 1 the output pin will go LOW
for ONE clock cycle only and then return HIGH. This cycle repeats
continuously without the need to re-program the count value.
Mode 3
When programmed the output pin will toggle each time the count register
decrements to its base level from the value programmed into it. If the count
value loaded is an odd number then the counter will reach zero before the output
pin toggles. This mode therefore acts as a frequency divider with an
approximate 1:1 mark-space ratio.
Mode 4
This mode is similar to mode 2 but the output pin pulses when the count reaches
zero instead of 1.
Mode 5
This mode is similar to mode 4 except that the count sequence is triggered by
the gate line. The gate lines are permanently enabled on the PCI-ADC.
Note that Counter / Timer interrupts are generated on the falling edge of the
timer outputs. This may limit the modes in which the timers can be operated as
interrupt sources.
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