參數(shù)資料
型號: PCI-ADC
英文描述: MULTIFUNKTIONSKARTE 44 KANAL PCI BUS
中文描述: MULTIFUNKTIONSKARTE 44卡納爾PCI總線
文件頁數(shù): 19/35頁
文件大?。?/td> 124K
代理商: PCI-ADC
Chapter 3
Programming Details
Page 11
Blue Chip Technology Ltd.
01270193.doc
Page 11
The major gain errors are associated with the A-D converter and not with the
input gain stages. The major offset errors are associated with the input gain
stages and not with the A-D converter. This is why the zero samples (used to
determine offsets) are measured at the required gain, whilst the full scale
samples (used to determine gain errors) are measured at minimum gain.
Note that when reading either the calibration zero or positive input, the channel
number stamped on the returned value is not meaningful.
Analogue Input Status
To determine the operating status of the analogue input section, the analogue
input status register is available at Base + 0E
h
. This register allows access to
the status of the A-D converter ‘busy’ flag, the ‘FIFO full’ flag, the ‘FIFO half
full’ flag, and the ‘FIFO empty’ flag.
Analogue Input Status Register
(Base 2 + 0E
h
) Read only
Function
Bit no.
b7..b3
b3
Not used (set to zero)
FIFO ‘Full’ Flag:-
0 = Not Full.
1 = Full.
0 = Not Half Full.
1 = Half Full.
0 = Not Empty.
1 = Empty.
0 = Conversion complete
1 = Conversion in progress
b2
FIFO ‘Half Full’ Flag:-
b1
FIFO ‘Empty’ Flag:-
b0
A-D Converter ‘Busy’ flag:-
Once the FIFO is full, conversions may continue to take place but will be
discarded. The FIFO prevents the storage of further values whilst the ‘Full’ flag
is asserted. Reading one value from the FIFO will negate the Full flag and
allow one more conversion to be stored, which will not be sequential with the
previously stored values. To avoid this situation occurring, it is recommended
that the ‘Half Full’ flag be used to initiate FIFO reads.
Reading an empty FIFO will return a value 0FFFF
h.
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