參數(shù)資料
型號: PCF8833U
廠商: NXP Semiconductors N.V.
英文描述: STN RGB - 132 X 132 X 3 driver
中文描述: 超扭曲的RGB - 132 × 132 × 3驅(qū)動(dòng)程序
文件頁數(shù): 92/112頁
文件大?。?/td> 469K
代理商: PCF8833U
2003 Feb 14
92
Philips Semiconductors
Objective specification
STN RGB - 132
×
132
×
3 driver
PCF8833
15.9
Programming specification
For programming OTP cells, the V
OTP(gate)
and V
OTP(drain)
voltages have to be applied as indicated in Fig.57. Voltages
V
OTP(gate)
and V
OTP(drain)
can be applied at the same time or can have a staggered sequence as indicated by cases
a and b of Fig.57.
Depending on the series resistance in the supply wires, up to 16 OTP bits can be programmed at the same time. Each
OTP cell can only be programmed once.
Table 98
Programming specification (see Fig.57)
Note
1.
The voltage drop across the ITO track and any connector must be taken into account to guarantee a sufficiently high
voltage at the chip pins.
SYMBOL
PARAMETER
CONDITION
MIN.
TYP.
MAX.
UNIT
V
OTP(gate)
voltage applied to V
OTP(gate)
pin
relative to V
SS1
programming active;
note 1
programming inactive
programming active;
note 1
programming inactive
tbf
8
tbf
V
tbf
tbf
0
8
tbf
tbf
V
V
V
OTP(drain)
voltage applied to V
OTP(drain)
pin
relative to V
SS1
tbf
tbf
0
100
tbf
tbf
V
μ
A
I
OTP(gate)
current drawn by V
OTP(gate)
during
programming
current drawn by V
OTP(drain)
during
programming
ambient temperature during
programming
set-up time of OPE as a function of
V
OTP(gate)
and V
OTP(drain)
hold time of OPE as a function of
V
OTP(gate)
and V
OTP(drain)
pulse width of programming voltage
I
OTP(drain)
per programmed OTP
cell
tbf
500
tbf
μ
A
T
amb(prog)
0
25
40
°
C
t
OPESU
V
OTP(gate)
and
V
OTP(drain)
> 0 V
V
OTP(gate)
and
V
OTP(drain)
> 0 V
1
ms
t
OPEHD
1
ms
t
WRITEPW
45
50
55
ms
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