參數(shù)資料
型號(hào): PCF8833U
廠商: NXP Semiconductors N.V.
英文描述: STN RGB - 132 X 132 X 3 driver
中文描述: 超扭曲的RGB - 132 × 132 × 3驅(qū)動(dòng)程序
文件頁數(shù): 13/112頁
文件大?。?/td> 469K
代理商: PCF8833U
2003 Feb 14
13
Philips Semiconductors
Objective specification
STN RGB - 132
×
132
×
3 driver
PCF8833
6.2
Function set
6.2.1
N
O OPERATION
No operation (NOP) has no effect on internal data or settings. However, it can be used to terminate data transfer (read
and write).
Table 3
No operation command bits
D/C
7
6
5
4
3
2
1
0
DEFAULT
0
0
0
0
0
0
0
0
0
00H
6.2.2
R
ESET
The PCF8833 has a hardware and a software reset. After
power-upahardwarereset(pinRES)mustbeapplied;see
Fig.50. The hardware and software resets give the same
results. After a reset, the chip has the following state:
All LCD outputs are set to V
SS
(display off)
RAM data unchanged
Power-down mode (Sleep_IN)
Command register set to default states; see Table 4
Interface pins are set to inputs.
After a reset, care must be taken with respect to the reset
timing constraints (see Fig.50) when the PCF8833 is
powered-up. The power-up must be done by sending the
Sleep_OUT command.
After a power-up the display RAM content is undefined.
Neither a hardware reset nor a software reset changes the
data that is stored in the display RAM. Sending display
data must stop 160 ns before issuing a hardware reset,
otherwise the last word written to the display RAM may be
corrupted. The row and column outputs are tied to V
SS1
with a reset because power-down (Sleep_IN) is in the
reset state.
Table 4
Reset state after hardware and software reset
COMMAND
DESCRIPTION
RESET STATE
Sleep_IN
INVOFF
BSTRON
DISPON
TEOFF
IDMOFF
NORON
V
MY
RGB
MX
LAO
BRS
TRS
FINV
DOR
TCDFE
TCVOPE
EC
PCF8833 is in Sleep_IN mode (booster and display are switched off)
display inversion is off
when Sleep_OUT is active; booster is switched on
when Sleep_OUT is active; display is turned on
tearing effect line pulse is turned off
Idle mode is turned off (4 kbyte colour mode, not 8-colour mode)
Normal mode is active, not Scroll or Partial mode
RAM write in X direction
no mirror Y
colour order is RGB
no mirror X
line address order (top to bottom)
bottom rows are not mirrored; note 1
top rows are not mirrored; note 1
super frame inversion is on
normal data order
DF temperature compensation switched on
VOP temperature compensation switched on
internal oscillator
0
0
0
0
0
0
0
1
0
1
1
0
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