參數(shù)資料
型號(hào): PCF8833U
廠商: NXP Semiconductors N.V.
英文描述: STN RGB - 132 X 132 X 3 driver
中文描述: 超扭曲的RGB - 132 × 132 × 3驅(qū)動(dòng)程序
文件頁數(shù): 5/112頁
文件大?。?/td> 469K
代理商: PCF8833U
2003 Feb 14
5
Philips Semiconductors
Objective specification
STN RGB - 132
×
132
×
3 driver
PCF8833
5
PINNING
SYMBOL
PAD
TYPE
DESCRIPTION
R95 to R64
C0 to C395
R0 to R31
R63 to R32
RES
2 to 33
34 to 429
430 to 461
464 to 495
496
O
O
O
O
I
LCD row driver outputs
LCD column driver outputs
LCD row driver outputs
LCD row driver outputs
external reset; this signal will reset the device and must be applied to properly
initialize the chip (active LOW)
tearing line (in Normal mode it is always an output)
system ground
system ground
chip select parallel interface or serial chip enable (active LOW)
logic supply voltage
V
DD2
and V
DD3
are the supply voltage pins for the internal voltage generator
including the temperature compensation circuits; V
DD2
and V
DD3
can be
connected together but in this case care must be taken to respect the supply
voltage range (see Chapter 13); V
DD1
is used as the supply for the rest of the
chip. V
DD1
can be connected together with V
DD2
and V
DD3
but in this case care
must also be taken to respect the supply voltage range; see Chapter 13. V
DD2
and V
DD3
must not be applied before V
DD1.
TE
V
SS1
V
SS2
CS/SCE
V
DD1
V
DD3
V
DD2
497
O/I
PS
PS
I
PS
PS
PS
498 to 507
508 to 517
518
519 to 524
525 to 529
530 to 539
If the internal voltage generator is not used, pins V
DD2
and V
DD3
must be
connected to V
DD1
.
8-bit parallel data; in Serial mode tie to V
SS1
or V
DD1
8-bit parallel data; in Serial mode tie to V
SS1
or V
DD1
8-bit parallel data; in Serial mode tie to V
SS1
or V
DD1
8-bit parallel data; in Serial mode tie to V
SS1
or V
DD1
8-bit parallel data; in Serial mode tie to V
SS1
or V
DD1
8-bit parallel data; in Serial mode tie to V
SS1
or V
DD1
8-bit parallel data; in Serial mode tie to V
SS1
or V
DD1
8-bit parallel data or serial data input
serial data output; in Parallel mode tie to V
DD1
, V
SS1
or D0
data/command indicator parallel interface or serial clock
write clock parallel interface; in Serial mode tie to V
DD1
(active LOW)
read clock parallel interface; in Serial mode tie to V
DD1
(active LOW)
set serial or parallel interface mode PS1 and PS2 must tied to either V
SS1
or
V
DD1
set serial or parallel interface mode PS1 and PS2 must tied to either V
SS1
or
V
DD1
set serial or parallel interface mode PS1 and PS2 must tied to either V
SS1
or
V
DD1
D7
D3
D6
D2
D5
D1
D4
D0/SDIN
SDOUT
D/C/SCLK
WR
RD
PS0
540
541
542
543
544
545
546
547
548
549
550
551
552
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
I
I
PS1
553
I
PS2
554
I
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