參數(shù)資料
型號: PCF8570
廠商: NXP Semiconductors N.V.
英文描述: 256 x 8-bit static low-voltage RAM with I2C-bus interface
中文描述: 256 × 8位靜態(tài)低電壓內(nèi)存具有I2C總線接口
文件頁數(shù): 9/20頁
文件大小: 140K
代理商: PCF8570
1999 Jan 06
9
Philips Semiconductors
Product specification
256
×
8-bit static low-voltage RAM with
I
2
C-bus interface
PCF8570
11 DC CHARACTERISTICS
V
DD
= 2.5 to 6.0 V; V
SS
= 0 V; T
amb
=
40 to +85
°
C; unless otherwise specified.
Notes
1.
The Power-on reset circuit resets the I
2
C-bus logic when V
DD
< V
POR
. The status of the device after a Power-on reset
condition can be tested by sending the slave address and testing the acknowledge bit.
If the input voltages are a diode voltage above or below the supply voltage V
DD
or V
SS
an input current will flow; this
current must not exceed
±
0.5 mA.
2.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
V
DD
I
DD
supply voltage
supply current
standby mode
2.5
6.0
V
V
I
= V
DD
or V
SS
;
f
SCL
= 0 Hz;
T
amb
=
25 to +70
°
C
V
I
= V
DD
or V
SS
;
f
SCL
= 100 Hz
note 1
5
μ
A
operating mode
200
μ
A
V
POR
Power-on reset voltage
1.5
1.9
2.3
V
Inputs, input/output SDA
V
IL
V
IH
I
OL
I
LI
LOW level input voltage
HIGH level input voltage
LOW level output current
input leakage current
note 2
note 2
V
OL
= 0.4 V
V
I
= V
DD
or V
SS
0.8
0.7V
DD
3
1
0.3V
DD
V
DD
+ 0.8 V
+1
V
mA
μ
A
Inputs A0, A1, A2 and TEST
I
LI
input leakage current
V
I
= V
DD
or V
SS
250
+250
nA
Inputs SCL and SDA
C
i
input capacitance
V
I
= V
SS
7
pF
Low V
DD
data retention
V
DDR
I
DDR
supply voltage for data retention
supply current
1
6
5
2
V
μ
A
μ
A
V
DDR
= 1 V
V
DDR
= 1 V;
T
amb
=
25 to +70
°
C
Power-saving mode
(see Figs 13 and 14)
I
DDR
t
HD2
supply current
recovery time
TEST = V
DD
; T
amb
= 25
°
C
50
50
400
nA
μ
s
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