參數(shù)資料
型號(hào): PCF8570
廠商: NXP Semiconductors N.V.
英文描述: 256 x 8-bit static low-voltage RAM with I2C-bus interface
中文描述: 256 × 8位靜態(tài)低電壓內(nèi)存具有I2C總線接口
文件頁(yè)數(shù): 10/20頁(yè)
文件大小: 140K
代理商: PCF8570
1999 Jan 06
10
Philips Semiconductors
Product specification
256
×
8-bit static low-voltage RAM with
I
2
C-bus interface
PCF8570
12 AC CHARACTERISTICS
All timing values are valid within the operating supply voltage and ambient temperature range and reference to V
IL
and
V
IH
with an input voltage swing of V
SS
to V
DD
.
Note
1.
A detailed description of the I
2
C-bus specification, with applications, is given in brochure “The I
2
C-bus and how to
use it” This brochure may be ordered using the code 9398 393 40011.
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
I
2
C-bus timing
(see Fig.10; note 1)
f
SCL
t
SP
t
BUF
t
SU;STA
t
HD;STA
t
LOW
t
HIGH
t
r
t
f
t
SU;DAT
t
HD;DAT
t
VD;DAT
t
SU;STO
SCL clock frequency
tolerable spike width on bus
bus free time
START condition set-up time
START condition hold time
SCL LOW time
SCL HIGH time
SCL and SDA rise time
SCL and SDA fall time
data set-up time
data hold time
SCL LOW-to-data out valid
STOP condition set-up time
4.7
4.7
4.0
4.7
4.0
250
0
4.0
100
100
1.0
0.3
3.4
kHz
ns
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
ns
ns
μ
s
μ
s
Fig.10 I
2
C-bus timing diagram; rise and fall times refer to V
IL
and V
IH
.
handbook, full pagewidth
PROTOCOL
SCL
SDA
MBD820
BIT 0
LSB
(R/W)
tHD;STA
tSU;DAT
tHD;DAT
tVD;DAT
tSU;STO
tf
r
t
tBUF
tSU;STA
tLOW
tHIGH
1 / fSCL
START
CONDITION
(S)
BIT 7
MSB
(A7)
BIT 6
(A6)
ACKNOWLEDGE
(A)
STOP
CONDITION
(P)
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