參數(shù)資料
型號: PCF8570
廠商: NXP Semiconductors N.V.
英文描述: 256 x 8-bit static low-voltage RAM with I2C-bus interface
中文描述: 256 × 8位靜態(tài)低電壓內(nèi)存具有I2C總線接口
文件頁數(shù): 6/20頁
文件大?。?/td> 140K
代理商: PCF8570
1999 Jan 06
6
Philips Semiconductors
Product specification
256
×
8-bit static low-voltage RAM with
I
2
C-bus interface
PCF8570
8.3
System configuration
A device generating a message is a ‘transmitter’, a device receiving a message is the ‘receiver’. The device that controls
the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’.
Fig.5 System configuration.
MBA605
MASTER
TRANSMITTER /
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER /
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER /
RECEIVER
SDA
SCL
8.4
Acknowledge
The number of data bytes transferred between the start
and stop conditions from transmitter to receiver is
unlimited. Each byte of eight bits is followed by an
acknowledge bit. The acknowledge bit is a HIGH level
signal put on the bus by the transmitter during which time
the master generates an extra acknowledge related clock
pulse. A slave receiver which is addressed must generate
an acknowledge after the reception of each byte. Also a
master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the
slave transmitter.
The device that acknowledges must pull down the SDA
line during the acknowledge clock pulse, so that the SDA
line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times
must be taken into consideration). A master receiver must
signal an end of data to the transmitter by not generating
an acknowledge on the last byte that has been clocked out
of the slave. In this event the transmitter must leave the
data line HIGH to enable the master to generate a stop
condition.
Fig.6 Acknowledgement on the I
2
C-bus.
handbook, full pagewidth
MBA606 - 1
START
condition
S
SCL FROM
MASTER
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
clock pulse for
acknowledgement
1
2
8
9
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