- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄367818 > PCF8566 (NXP Semiconductors N.V.) Universal LCD driver for low multiplex rates PDF資料下載
參數(shù)資料
| 型號： | PCF8566 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Universal LCD driver for low multiplex rates |
| 中文描述： | 通用LCD驅(qū)動器的低復(fù)用率 |
| 文件頁數(shù)： | 19/40頁 |
| 文件大?。?/td> | 243K |
| 代理商： | PCF8566 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當(dāng)前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁
1998 May 04
19
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8566
7.5
PCF8566 I
2
C-bus controller
The PCF8566 acts as an I
2
C-bus slave receiver. It does
not initiate I
2
C-bus transfers or transmit data to an I
2
C-bus
master receiver. The only data output from the PCF8566
are the acknowledge signals of the selected devices.
Device selection depends on the I
2
C-bus slave address,
on the transferred command data and on the hardware
subaddress.
In single device applications, the hardware subaddress
inputs A0, A1 and A2 are normally left open-circuit or tied
to V
SS
which defines the hardware subaddress 0.
In multiple device applications A0, A1 and A2 are left
open-circuit or tied to V
SS
or V
DD
according to a binary
coding scheme such that no two devices with a common
I
2
C-bus slave address have the same hardware
subaddress.
In the power-saving mode it is possible that the PCF8566
is not able to keep up with the highest transmission rates
when large amounts of display data are transmitted. If this
situation occurs, the PCF8566 forces the SCL line LOW
until its internal operations are completed. This is known
as the ‘clock synchronization feature’ of the I
2
C-bus and
serves to slow down fast transmitters. Data loss does not
occur.
7.6
Input filters
To enhance noise immunity in electrically adverse
environments, RC low-pass filters are provided on the
SDA and SCL lines.
7.7
I
2
C-bus protocol
Two I
2
C-bus slave addresses (0111110 and 0111111) are
reserved for PCF8566. The least-significant bit of the slave
address that a PCF8566 will respond to is defined by the
level tied at its input SA0 (pin 10). Therefore, two types of
PCF8566 can be distinguished on the same I
2
C-bus which
allows:
1.
Up to 16 PCF8566s on the same I
2
C-bus for very large
LCD applications
2.
The use of two types of LCD multiplex on the same
I
2
C-bus.
The I
2
C-bus protocol is shown in Fig.15. The sequence is
initiated with a START condition (S) from the I
2
C-bus
master which is followed by one of the two PCF8566 slave
addresses available. All PCF8566s with the corresponding
SA0 level acknowledge in parallel the slave address but all
PCF8566s with the alternative SA0 level ignore the whole
I
2
C-bus transfer. After acknowledgement, one or more
command bytes (m) follow which define the status of the
addressed PCF8566s. The last command byte is tagged
with a cleared most-significant bit, the continuation bit C.
The command bytes are also acknowledged by all
addressed PCF8566s on the bus.
After the last command byte, a series of display data bytes
(n) may follow. These display data bytes are stored in the
display RAM at the address specified by the data pointer
and the subaddress counter. Both data pointer and
subaddress counter are automatically updated and the
data are directed to the intended PCF8566 device.
The acknowledgement after each byte is made only by the
(A0, A1, A2) addressed PCF8566. After the last display
byte, the I
2
C-bus master issues a STOP condition (P).
7.8
Command decoder
The command decoder identifies command bytes that
arrive on the I
2
C-bus. All available commands carry a
continuation bit C in their most-significant bit position
(see Fig.16). When this bit is set, it indicates that the next
byte of the transfer to arrive will also represent a
command.
If the bit is reset, it indicates the last command byte of the
transfer. Further bytes will be regarded as display data.
The five commands available to the PCF8566 are defined
in Table 5.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCF8573 | Clock/calendar with Power Fail Detector |
| PCF8573P | Clock/calendar with Power Fail Detector |
| PCF8573T | Clock/calendar with Power Fail Detector |
| PCF8574 | Remote 8-bit I/O expander for I2C-bus |
| PCF8578 | LCD row/column driver for dot matrix graphic displays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCF8566P | 制造商:NXP Semiconductors 功能描述:LCD DRIVER LOW-MUX 40DIP 制造商:NXP Semiconductors 功能描述:LCD DRIVER, LOW-MUX, 40DIP |
| PCF8566P,112 | 功能描述:LCD 驅(qū)動器 LCD DVR UNVRSL LOW-MUX RoHS:否 制造商:Maxim Integrated 數(shù)位數(shù)量:4.5 片段數(shù)量:30 最大時鐘頻率:19 KHz 工作電源電壓:3 V to 3.6 V 最大工作溫度:+ 85 C 最小工作溫度:- 20 C 封裝 / 箱體:PDIP-40 封裝:Tube |
| PCF8566P-1 | 制造商:PHILIPS-SEMI 功能描述: |
| PCF8566PN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Display Driver |
| PCF8566T | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Universal LCD driver for low multiplex rates |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。