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參數(shù)資料
| 型號： | PCF8566 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Universal LCD driver for low multiplex rates |
| 中文描述： | 通用LCD驅(qū)動器的低復(fù)用率 |
| 文件頁數(shù)： | 17/40頁 |
| 文件大?。?/td> | 243K |
| 代理商： | PCF8566 |
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1998 May 04
17
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8566
7
I
2
C-BUS DESCRIPTION
The I
2
C-bus is for 2-way, 2-line communication between
different ICs or modules. The two lines are a serial data
line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when
connected to the output stages of a device. Data transfer
may be initiated only when the bus is not busy.
7.1
Bit transfer
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this time will be interpreted as control signals.
7.2
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line while the
clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH is defined as the STOP condition (P).
7.3
System configuration
A device generating a message is a ‘transmitter’, a device
receiving a message is a ‘receiver’. The device that
controls the message is the ‘master’ and the devices which
are controlled by the master are the ‘slaves’.
7.4
Acknowledge
The number of data bytes transferred between the START
and STOP conditions from transmitter to receiver is not
limited. Each byte is followed by one acknowledge bit.
The acknowledge bit is a HIGH level put on the bus by the
transmitter whereas the master generates an extra
acknowledge related clock pulse. A slave receiver which is
addressed must generate an acknowledge after the
reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has
been clocked out of the slave transmitter. The device that
acknowledges has to pull down the SDA line during the
acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related
clock pulse, set up and hold times must be taken into
account. A master receiver must signal an end of data to
the transmitter by not generating an acknowledge on the
last byte that has been clocked out of the slave. In this
event the transmitter must leave the data line HIGH to
enable the master to generate a STOP condition.
Fig.11 Bit transfer.
MBA607
data line
stable;
data valid
change
of data
allowed
SDA
SCL
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCF8566P | 制造商:NXP Semiconductors 功能描述:LCD DRIVER LOW-MUX 40DIP 制造商:NXP Semiconductors 功能描述:LCD DRIVER, LOW-MUX, 40DIP |
| PCF8566P,112 | 功能描述:LCD 驅(qū)動器 LCD DVR UNVRSL LOW-MUX RoHS:否 制造商:Maxim Integrated 數(shù)位數(shù)量:4.5 片段數(shù)量:30 最大時鐘頻率:19 KHz 工作電源電壓:3 V to 3.6 V 最大工作溫度:+ 85 C 最小工作溫度:- 20 C 封裝 / 箱體:PDIP-40 封裝:Tube |
| PCF8566P-1 | 制造商:PHILIPS-SEMI 功能描述: |
| PCF8566PN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Display Driver |
| PCF8566T | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Universal LCD driver for low multiplex rates |
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