參數(shù)資料
型號(hào): PCF8549
廠商: NXP Semiconductors N.V.
英文描述: 65 x 102 pixels matrix LCD driver
中文描述: 65 × 102像素矩陣LCD驅(qū)動(dòng)器
文件頁數(shù): 22/36頁
文件大?。?/td> 271K
代理商: PCF8549
1997 Nov 21
22
Philips Semiconductors
Product specification
65
×
102 pixels matrix LCD driver
PCF8549
AC CHARACTERISTICS
Table 8
V
DD1
= 1.5 to 6 V; V
DD2/2_HV
= 2.4 to 5.0 V; V
DD2
= V
DD2_HV
; V
SS1
= V
SS2
= V
SS2_HV
= 0 V; V
LCD
= 7 to 16 V;
T
amb
=
40 to +85
°
C; unless otherwise specified.
Note
1.
2.
3.
Duty cycle of 50 +/-5%.
The rise and fall times specified here refer to the driver device (i.e. not PCF8549) and are part of the general fast
I
2
C-bus specification. When PCF8549 asserts an acknowledge on SDA, the minimum fall time is 10ns. C
b
=
capacitive load per bus line.
The device inputs SDA and SCL are filtered and will reject spikes on the bus lines of width < t
SW(max)
.
Not tested in production
Only for VDD1= 2V to 6V
4.
5.
6.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
f
OSC
f
EXT
t
start
f
FRAME
t
VHRL
t
PWRES
oscillator frequency
external clock frequency
oscillator start up time
frame frequency
VDD to RES Low
reset low pulse width
19
10
32
32
450
62
64
64
1600
1
kHz
kHz
us
Hz
ms
ns
(2)
(5)
f
EXT
= 32 kHz;
(1)
(5)
400
I
2
C timing characteristics
f
SCLK
t
LOW
t
HIGH
t
SU;Data
t
HD;Data
t
R
t
F
c
b
SCL clock frequency
SCL clock low period
SCL clock high period
Data set-up time
Data hold time
SCL and SDA rise time
SCL and SDA fall time
Capacitive load represented by each
bus line
setup time for a repeated START con-
dition
start condition hold time
data set-up time
data hold-time
setup time for STOP condition
tolerable spike width on bus
BUS free time between a STOP and
START condition
(6)
DC
1.3
0.6
100
0
20 + 0.1 Cb
20 + 0.1 Cb
400
0.9
300
300
400
kHz
us
us
ns
us
ns
ns
pF
(3)
(3)
t
SU;STA
0.6
us
t
HD;STA
t
SU;DAT
t
HD;DAT
t
SU;STO
t
SW
t
BUF
0.6
100
0
0.6
1.3
50
us
ns
ns
us
ns
us
(4)
f
FRAME
f
520
=
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