參數(shù)資料
型號(hào): PCF8549
廠商: NXP Semiconductors N.V.
英文描述: 65 x 102 pixels matrix LCD driver
中文描述: 65 × 102像素矩陣LCD驅(qū)動(dòng)器
文件頁(yè)數(shù): 13/36頁(yè)
文件大?。?/td> 271K
代理商: PCF8549
1997 Nov 21
13
Philips Semiconductors
Product specification
65
×
102 pixels matrix LCD driver
PCF8549
I
2
C-bus protocol
The PCF8549 supports both read and write access. The
R/W bit is part of the slave address.
Before any data is transmitted on the I
2
C-bus, the device
which should respond is addressed first. Two 7-bit slave
addresses (0111100 and 0111101) are reserved for the
PCF8549. The least significant bit of the slave address is
set by connecting the input SA0 to either logic 0 (V
SS1
) or
1 (V
DD1
).
The I
2
C-bus protocol is illustrated in Fig.13.
The sequence is initiated with a START condition (S) from
the I
2
C-bus master which is followed by the slave address.
All slaves with the corresponding address acknowledge in
parallel, all the others will ignore the I
2
C-bus transfer. After
acknowledgement, one or more command words follow
which define the status of the addressed slaves. A
command word consists of a control byte, which defines
Co and D/C, plus a data byte (see Fig.13 and Table 1).
The last control byte is tagged with a cleared most
significant bit, the continuation bit Co. After a control byte
with a cleared Co-bit, only data bytes will follow. The state
of the D/C-bit defines whether the data-byte is interpreted
as a command or as RAM-data.The control and data bytes
are also acknowledged by all addressed slaves on the bus.
After the last control byte, depending on the D/C bit
setting, either a series of display data bytes or command
data bytes may follow. If the D/C bit was set to ‘1’, these
display bytes are stored in the display RAM at the address
specified by the data pointer. The data pointer is
automatically updated and the data is directed to the
intended PCF8549 device. If the D/C bit of the last control
byte was set to ‘0’, these command bytes will be decoded
and the setting of the device will be changed according to
the received commands. The acknowledgement after
each byte is made only by the addressed slave. At the end
of the transmission the I
2
C-bus master issues a stop
condition (P).
If the R/W bit is set to one in the slave-address, the chip
will output data immediately after the slave-address
according to the D/C bit, which was sent during the last
write access. If no acknowledge is generated by the
master after a byte, the driver stops transferring data to the
master.
Fig.13 I
2
C-bus protocol.
S
A
0
S
A
A
DC
1
control byte
A
data byte
P
A
DC
0
control byte
A
data byte
1 1 1
0
0
1
slave address
2n > 0 bytes
1 byte
n > 0 bytes
MSB................. LSB
PCF8549
slave address
Co
Co
acknowledgement
from PCF8549
1 1 1
0
0
1
acknowledgement
from PCF8549
acknowledgement
from PCF8549
acknowledgement
from PCF8549
acknowledgement
from PCF8549
0
R
W
S
A
0
S
A
0
S
A
A
A
data byte
P
A
A
data byte
slave address
acknowledgement
from Master
1 1 1
0
0
1
acknowledgement
from Master
acknowledgement
from Master
acknowledgement
from Master
1
data byte
data byte
C
O
DC 0 0
0
0 0 0
A
Control Byte
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