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    • 參數(shù)資料
      型號(hào): PCF8549
      廠商: NXP Semiconductors N.V.
      英文描述: 65 x 102 pixels matrix LCD driver
      中文描述: 65 × 102像素矩陣LCD驅(qū)動(dòng)器
      文件頁(yè)數(shù): 11/36頁(yè)
      文件大小: 271K
      代理商: PCF8549
      1997 Nov 21
      11
      Philips Semiconductors
      Product specification
      65
      ×
      102 pixels matrix LCD driver
      PCF8549
      RAM access
      If the D/C bit is 1 the RAM can be accessed in both read
      and write access mode, depending on the R/W bit. The
      data is written to the RAM during the acknowledge cycle.
      I
      2
      C-BUS INTERFACE
      Characteristics of the I
      2
      C-bus
      The I
      2
      C-bus is for bi-directional, two-line communication
      between different ICs or modules. The two lines are a
      serial data line (SDA) and a serial clock line (SCL). Both
      lines must be connected to a positive supply via a pull-up
      resistor. Data transfer may be initiated only when the bus
      is not busy.
      B
      IT TRANSFER
      (see Fig.9)
      One data bit is transferred during each clock pulse. The
      data on the SDA line must remain stable during the HIGH
      Fig.8 Read modify write access.
      Set Address
      Set Read
      Modify Write Mode
      Read Data
      Write Data
      END
      Finished
      no
      yes
      period of the clock pulse as changes in the data line at this
      time will be interpreted as a control signal.
      S
      TART AND STOP CONDITIONS
      (see Fig.10)
      Both data and clock lines remain HIGH when the bus is not
      busy. A HIGH-to-LOW transition of the data line, while the
      clock is HIGH is defined as the START condition (S). A
      LOW-to-HIGH transition of the data line while the clock is
      HIGH is defined as the STOP condition (P).
      S
      YSTEM CONFIGURATION
      (see Fig.11)
      Transmitter: The device which sends the data to the bus
      Receiver: The device which receives the data from the
      bus
      Master: The device which initiates a transfer, generates
      clock signals and terminates a transfer
      Slave: The device addressed by a master
      Multi-Master: More than one master can attempt to
      control the bus at the same time without corrupting the
      message
      Arbitration: Procedure to ensure that, if more than one
      master simultaneously tries to control the bus, only one
      is allowed to do so and the message is not corrupted
      Synchronisation: Procedure to synchronize the clock
      signals of two or more devices.
      A
      CKNOWLEDGE
      (see Fig.12)
      Each byte of eight bits is followed by an acknowledge bit.
      The acknowledge bit is a HIGH signal put on the bus by
      the transmitter during which time the master generates an
      extra acknowledge related clock pulse. A slave receiver
      which is addressed must generate an acknowledge after
      the reception of each byte. Also a master receiver must
      generate an acknowledge after the reception of each byte
      that has been clocked out of the slave transmitter. The
      device that acknowledges must pull-down the SDA line
      during the acknowledge clock pulse, so that the SDA line
      is stable LOW during the HIGH period of the acknowledge
      related clock pulse (set-up and hold times must be taken
      into consideration). A master receiver must signal an end
      of data to the transmitter by not generating an
      acknowledge on the last byte that has been clocked out of
      the slave. In this event the transmitter must leave the data
      line HIGH to enable the master to generate a stop
      condition.
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      參數(shù)描述
      PCF8549U 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:65 x 102 pixels matrix LCD driver
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