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參數(shù)資料
| 型號： | PCF8535 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 65 x 133 pixel matrix driver |
| 中文描述： | 65 × 133像素矩陣驅(qū)動程序 |
| 文件頁數(shù)： | 7/52頁 |
| 文件大?。?/td> | 1765K |
| 代理商： | PCF8535 |
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1999 Aug 24
7
Philips Semiconductors
Objective specification
65
×
133 pixel matrix driver
PCF8535
6.1.2
C0
TO
C132
These pads output the display column signals.
6.1.3
V
SS1
AND
V
SS2
V
SS1
and V
SS2
must be connected together.
6.1.4
V
DD1
TO
V
DD3
V
DD1
is the logic supply. V
DD2
and V
DD3
are for the voltage
multiplier. For split power supplies V
DD2
and V
DD3
must be
connected together. If only one supply voltage is available,
all three supplies must be connected together.
6.1.5
V
LCDOUT
If, in the application, an external V
LCD
is used, V
LCDOUT
must be left open-circuit; otherwise (if the internal voltage
multiplier is enabled) the chip may be damaged. V
LCDOUT
should not be driven when V
DD1
is below its minimum
allowed value otherwise a low impedance path between
V
LCDOUT
and V
SS1
will exist.
6.1.6
V
LCDIN
This is the V
LCD
supply for when an external V
LCD
is used.
If the internal V
LCD
generator is used, then V
LCDOUT
and
V
LCDIN
must be connected together. V
LCDIN
should not be
driven when V
DD1
is below its minimum allowed value,
otherwise a low impedance path between V
LCDIN
and V
SS1
will exist.
6.1.7
V
LCDSENSE
This is the input to the internal voltage multiplier regulator.
It must be connected to V
LCDOUT
when the internal voltage
generator is used otherwise it may be left open-circuit.
V
LCDSENCE
should not be driven when V
DD1
is below its
minimum allowed value, otherwise a low impedance path
between V
LCDSENCE
and V
SS1
will exist.
6.1.8
SDA
I
2
C-bus serial data input.
6.1.9
SDAOUT
SDAOUT is the serial data acknowledge for the I
2
C-bus.
By connecting SDAOUT to SDA externally, the SDA line
becomes fully I
2
C-bus compatible. Having the
acknowledge output separated from the serial data line is
advantageous in Chip-On-Glass (COG) applications.
In COG applications where the track resistance from the
SDAOUT pad to the system SDA line can be significant, a
potential divider is generated by the bus pull-up resistor
and the Indium Tin Oxide (ITO) track resistance. It is
possible that during the acknowledge cycle the PCF8535
will not be able to create a valid logic 0 level. By splitting
the SDA input from the SDAOUT output the device could
be used in a mode that ignores the acknowledge bit.
In COG applications where the acknowledge cycle is
required or where read back is required, it is necessary to
minimizethetrackresistancefromtheSDAOUT padtothe
system SDA line to guarantee a valid LOW level.
6.1.10
SCL
I
2
C-bus serial clock input.
6.1.11
SA0
AND
SA1
Least significant bits of the I
2
C-bus slave address.
Table 1
Slave address; see note 1
Note
1.
The slave address is a concatination of the following
bits {01111, SA1, SA0 and R/W}.
6.1.12
OSC
If the on-chip oscillator is used this input must be
connected to V
DD1
or V
SS1
.
6.1.13
RES
External reset pad: when this pad is LOW the chip will be
reset; see Section 7.1. If an external reset is not required,
this pad must be tied to V
DD1
. Timing for the RES pad is
given in Chapter 12.
6.1.14
T1, T2, T3, T4
AND
T5
In applications T4 and T5 must be connected to V
SS
.
T1, T2 and T3 are to be left open-circuit.
SA1 AND SA0
MODE
SLAVE ADDRESS
0 and 0
write
read
write
read
write
read
write
read
78H
79H
7AH
7BH
7CH
7DH
7EH
7FH
0 and 1
1 and 0
1 and 1
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