參數(shù)資料
型號(hào)： PCF8535
廠商： NXP Semiconductors N.V.
英文描述： 65 x 133 pixel matrix driver
中文描述： 65 × 133像素矩陣驅(qū)動(dòng)程序
文件頁(yè)數(shù)： 31/52頁(yè)
文件大小： 1765K
代理商： PCF8535
1999 Aug 24
31
Philips Semiconductors
Objective specification
65
×
133 pixel matrix driver
PCF8535
7.17.2
I
2
C-
BUS PROTOCOL
The PCF8535 is a slave receiver/transmitter. If data is to
be read from the device the SDAOUT pad must be
connected, otherwise SDAOUT is unused.
Before any data is transmitted on the I
2
C-bus, the device
which should respond is addressed. Four slave
addresses,0111100,0111101,0111110and 0111111are
reserved for the PCF8535. The Least Significant Bits
(LSBs) of the slave address is set by connecting
SA1 and SA0 to either logic 0 (V
SS
) or logic 1 (V
DD
).
A sequence is initiated with a START condition (S) from
the I
2
C-bus master which is followed by the slave address.
All slaves with the corresponding address acknowledge in
parallel, all the others will ignore the I
2
C-bus transfer.
After the acknowledgement cycle of a write, a control byte
follows which defines the destination for the forthcoming
data byte and the mode for subsequent bytes. For a read,
thePCF8535willimmediatelystarttooutputtherequested
data until a NOT acknowledge is transmitted by the
master. The sequence should be terminated by a STOP in
the event that no further access is required for the time
being, or by a RE-START, should further access be
required.
For ease of operation a continuation bit, Co, has been
included. This bit allows the user to set-up the chip
configurationandtransmitRAMdatainoneaccess.Adata
selection bit, D/C, defines the destination for data. These
bits are contained in the control byte. DB5 to DB0 should
be set to logic 0. These bits are reserved for future
expansion.
Table 19
Co and D/C definitions
An example of a write access is given in Fig.19. Here, multiple instruction data is sent, followed by multiple display bytes.
An example of a read access is given in Fig.20.
BIT
0/1
R/W
ACTION
Co
0
n.a.
last control byte to be sent: only a stream of data bytes are allowed to follow; this stream may
only be terminated by a STOP or RE-START condition
another control byte will follow the data byte unless a STOP or RE-START condition is received
data byte will be decoded and used to set up the device
data byte will return the contents of the currently selected status register
data byte will be stored in the display RAM
no provision for RAM read back is provided
1
0
D/C
0
1
0
1
1
Fig.19 Master transmits to slave receiver; write mode.
handbook, full pagewidth
MGS682
S 0 1 1 1 1
S
A
0
S
A
1
0 A
acknowledgement
from PCF8535
acknowledgement
from PCF8535
acknowledgement
from PCF8535
acknowledgement
from PCF8535
acknowledgement
from PCF8535
1
control byte
A
data byte
data byte
n
≥
0 bytes
1 byte
slave address
MSB . . . . . . . . . . . LSB
2n
≥
0 bytes
A
Co
update
data pointer
Co
R/W
0
A
A P
D/C
D/C
control byte
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