參數(shù)資料
型號： PCF8531
廠商： NXP Semiconductors N.V.
英文描述： 34×128 pixel matrix driver(34×128 像素矩陣驅(qū)動器)
中文描述： 34 × 128像素矩陣驅(qū)動器（34 × 128像素矩陣驅(qū)動器）
文件頁數(shù)： 20/44頁
文件大小： 212K
代理商： PCF8531
2000 Feb 11
20
Philips Semiconductors
Product specification
34
×
128 pixel matrix driver
PCF8531
9.2
I
2
C-bus protocol
This driver does not support ‘read’. The PCF8531 is a
slave receiver. Therefore, it only responds when R/W = 0
in the slave address byte.
Before any data is transmitted on the I
2
C-bus, the device
that should respond is addressed first. Two 7-bit slave
addresses (0111100 and 0111101) are reserved for the
PCF8531. The least significant bit of the slave address is
set by connecting the input SA0 to either logic 0 (V
SS
) or
logic 1 (V
DD
).
The I
2
C-bus protocol is illustrated in Fig.14.
The sequence is initiated with a START condition (S) from
the I
2
C-bus master, and is followed by the slave address.
All slaves with the corresponding address acknowledge in
parallel, all others ignore the I
2
C-bus transfer. After
acknowledgement, one or more command words follow,
which define the status of the addressed slaves.
A command word consists of a control byte, which defines
Co and RS, plus a data byte (see Fig.14 and Table 1).
The last control byte is tagged with a cleared most
significantbit,thecontinuationbit Co.Thecontrolanddata
bytes are also acknowledged by all addressed slaves on
the bus.
After the last control byte, depending on the RS bit setting,
either a series of display data bytes or command data
bytes may follow. If the RS bit was set to logic 1, these
display bytes are stored in the display RAM at the address
specified by the data pointer.
The data pointer is automatically updated and the data is
directed to the intended PCF8531 device. If the RS bit of
the last control byte was set to logic 0, these command
bytes will be decoded and the setting of the device will be
changed according to the received commands.
The acknowledgement after each byte is made only by the
addressed PCF8531. At the end of the transmission, the
I
2
C-bus master issues a STOP condition (P).
9.3
Command decoder
Pairs of bytes; information in the second byte, the first
byte determines whether information is display or
instruction data
Stream of information bytes after Co = 0; display or
instruction data, depending on last RS (Register
Selection).
The command decoder identifies command words that
arrive on the I
2
C-bus. The most significant bit of a control
byte is the continuation bit Co. If this bit is logic 1, it
indicates that only one data byte (either command or RAM
data) will follow. If this bit is logic 0, it indicates that a series
of data bytes (either command or RAM data) may follow.
The DB6 bit of a control byte is the RAM data/command
bit RS. When this bit is at logic 1, it indicates that another
RAM data byte will be transferred next. If the bit is at
logic 0, it indicates that another command byte will be
transferred next.
handbook, full pagewidth
MGS474
S
0
1
1
1
1
0
SA0
A
slave address
R/W
Co
RS
X
X
X
X
X
X
control byte
Fig.14 Slave address and control byte.
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相關代理商/技術參數(shù)
參數(shù)描述
PCF8531_1008 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:34 x 128 pixel matrix driver
PCF8531_11 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:34 x 128 pixel matrix driver Single-chip LCD controller and driver
PCF8531U 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Display Driver
PCF8531U/2 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:34 x 128 pixel matrix driver
PCF8531U/2/F1 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Display Driver
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