參數(shù)資料
型號: PCF8531
廠商: NXP Semiconductors N.V.
英文描述: 34×128 pixel matrix driver(34×128 像素矩陣驅(qū)動器)
中文描述: 34 × 128像素矩陣驅(qū)動器(34 × 128像素矩陣驅(qū)動器)
文件頁數(shù): 13/44頁
文件大?。?/td> 212K
代理商: PCF8531
2000 Feb 11
13
Philips Semiconductors
Product specification
34
×
128 pixel matrix driver
PCF8531
8.18.2
F
UNCTION SET
8.18.2.1
PD
When PD = 1, the Power-down mode of the LCD driver is
active:
All LCD outputs at V
SS
(display off)
Power-on reset detection active, oscillator off
V
LCD
can be disconnected
I
2
C-bus is operational, commands can be executed
RAM contents not cleared; RAM data can be written
Register settings remain unchanged.
8.18.2.2
V
When V = 0 the horizontal addressing is selected.
The data is written into the DDRAM as shown in Fig.7.
When V = 1 the vertical addressing is selected. The data
is written into the DDRAM as shown in Fig.6. Icon data is
written independently of V when Y address is 5.
8.18.3
S
ET
Y
ADDRESS
Bits Y
2
, Y
1
and Y
0
define the Y address vector of the
display RAM.
Table 1
Yaddress
8.18.4
S
ET
X
ADDRESS
The X address points to the columns. The range of X is
0 to 127 (7FH).
8.18.5
S
ET MULTIPLEX RATE
M[1:0] selects the multiplex rate (see Table 8).
8.18.6
D
ISPLAY CONTROL
(D, E
AND
IM)
Bits D and E select the display mode (see Table 6). Bit IM
sets the display to icon mode.
8.18.7
S
ET BIAS SYSTEM
Different multiplex rates require different bias settings.
These are programmed by BS[2:0], which sets the binary
number n. The optimum value for n is given by
Supported values of n are given in Table 2. Table 3 shows
the intermediate bias voltages.
Y
2
0
0
0
0
1
1
Y
1
0
0
1
1
0
0
Y
0
0
1
0
1
0
1
BANK
0
1
2
3
4
5 (icons)
n
Mux rate
3
=
Table 2
Programming the required bias system
BS[2]
BS[1]
BS[0]
n
BIAS SYSTEM
COMMENT
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
7
6
5
4
3
2
1
0
1
11
1
10
1
9
1
8
1
7
1
6
1
5
1
4
recommended for 1 : 34
recommended for 1 : 26
recommended for 1 : 17
recommended for icon mode
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