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參數(shù)資料
| 型號： | PCF2105MU |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | LCD controller/driver |
| 中文描述： | LCD控制器/驅動器 |
| 文件頁數(shù)： | 6/48頁 |
| 文件大?。?/td> | 289K |
| 代理商： | PCF2105MU |
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1998 Jul 30
6
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
7.8
OSC: oscillator
When the on-chip oscillator is used, pad OSC must be
connected to V
DD
. An external clock signal, if used, is input
at pad OSC.
7.9
SCL: serial clock line
Pad SCL is input for the I
2
C-bus clock signal.
7.10
SDA: serial data line
Pad SDA is input/output for the I
2
C-bus data line.
7.11
SA0: address input
The hardware subaddress line is used to program the
device subaddress for 2 different PCF2105s on the same
I
2
C-bus.
7.12
T1: test input
Pad T1 must be connected to V
SS
. Not user accessible.
8
FUNCTIONAL DESCRIPTION
Figure 1 shows the block diagram for the PCF2105.
Details are explained in subsequent sections.
8.1
LCD bias voltage generator
The intermediate bias voltages for the LCD are generated
on-chip. This removes the need for an external resistive
bias chain and significantly reduces the system power
consumption. The optimum levels depend on the multiplex
(MUX) rate and are selected automatically when the
number of lines in the display is defined.
The optimum value of the LCD operating voltage V
OP
depends on the MUX rate, the LCD threshold voltage V
th
and the number of bias levels. The relationships, together
with the discrimination ratio (D) are given in Table 1.
Using a 5-level bias scheme for MUX rate 1 : 16 allows
V
OP
< 5 V for most LCDs. The effect on the display
contrast is negligible.
Table 1
Optimum values for V
OP
MUX
RATE
NUMBER
OF BIAS
LEVELS
1 : 16
1 : 32
5
6
3.67
5.19
1.277
1.196
v
v
th
---------
D
V
off
V
=
8.2
Oscillator
The on-chip oscillator provides the clock signal for the
display system. No external components are required.
Pad OSC must be connected to V
DD
.
8.3
External clock
If an external clock is to be used, it must be input at
pad OSC. The resulting display frame frequency is given
f
2304
by
A clock signal must always be present, otherwise the LCD
may be frozen in a DC state.
8.4
Power-on reset
The Power-on reset block initializes the chip after
power-on or power failure.
8.5
Registers
The PCF2105 has two 8-bit registers, an Instruction
Register (IR) and a Data Register (DR). The Register
Select (RS) signal determines which register will be
accessed.
The IR stores instruction codes such as ‘clear display’ and
‘cursor shift’, and address information for the DDRAM
and CGRAM. The system controller can write data to but
can not read data from the instruction register.
The DR temporarily stores data to be read from the
DDRAM and CGRAM. When reading, data from the
DDRAM or CGRAM (corresponding to the address in the
address counter) is written to the DR prior to being read by
the ‘read data’ instruction.
8.6
Busy flag
The Busy Flag (BF) indicates the free or busy status of the
PCF2105. Bit BF = 1 indicates that the chip is busy and
further instructions will not be accepted. The BF is output
at pad DB7 when bit RS = 0 and bit R/W = 1. Instructions
should only be written after checking that BF = 0 or waiting
for the required number of clock cycles.
8.7
Address Counter (AC)
The AC assigns addresses to the DDRAM and CGRAM for
reading and writing and is set by the instructions ‘set
CGRAM address’ and ‘set DDRAM address’. After a
read/write operation the AC is automatically incremented
or decremented by 1. The AC contents are output to the
bus (pads DB6 to DB0) when bit RS = 0 and bit R/W =1.
f
frame
------------
=
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