參數(shù)資料
型號： PCF2105MU
廠商： NXP Semiconductors N.V.
英文描述： LCD controller/driver
中文描述： LCD控制器/驅(qū)動器
文件頁數(shù)： 29/48頁
文件大?。?/td> 289K
代理商： PCF2105MU
1998 Jul 30
29
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
Notes
1.
2.
V
DD
= 5.0 V.
All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to
V
IL
and V
IH
with an input voltage swing of V
SS
to V
DD
.
C
L
= total capacitance of one bus line in pF and R = 100
.
A fast mode I
2
C-bus device can be used in a standard-mode I
2
C-bus system, but the requirement t
SU;DAT
≥
250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal.
If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
t
r(max)
+ t
SU;DAT
= 1000 + 250 = 1250 ns (according to the standard-mode I
2
C-bus specification) before the SCL line
is released.
A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
IH(min)
of the SCL
signal) in order to bridge the undefined region of the falling edge of SCL.
The maximum t
HD;DAT
has only to be met if the device does not stretch t
LOW
of the SCL signal.
3.
4.
5.
6.
Timing characteristics: I
2
C-bus interface;
note 2; see Fig.25
f
SCL
t
SW
t
BUF
t
SU;STA
SCL clock frequency
tolerable spike width on bus
bus free time
set-up time for a repeated START
condition
START condition hold time
SCL LOW time
SCL HIGH time
SCL and SDA rise time
SCL and SDA fall time
data set-up time
data hold time
set-up time for STOP condition
load capacitance for each bus line
1.3
0.6
400
50
kHz
ns
μ
s
μ
s
t
HD;STA
t
LOW
t
HIGH
t
r
t
f
t
SU;DAT
t
HD;DAT
t
SU;STO
C
L
0.6
1.3
0.6
100
0
0.6
20 + RC
L
20 + RC
L
300
300
0.9
400
μ
s
μ
s
μ
s
ns
ns
ns
μ
s
μ
s
pF
note 3
note 3
note 4
notes 5 and 6
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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