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參數資料
| 型號： | PCE84C487 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Microcontrollers for digital auto-sync and VST TV controller applications |
| 中文描述： | 微控制器的數字自動同步和VST電視控制器的應用 |
| 文件頁數： | 8/36頁 |
| 文件大?。?/td> | 168K |
| 代理商： | PCE84C487 |
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1996 Feb 21
8
Philips Semiconductors
Objective specification
Microcontrollers for digital auto-sync and
VST TV controller applications
PCE84C486; PCE84C487
Table 2
SDIP42 package
SYMBOL
PIN
DESCRIPTION
DP20/SDA
P10/SCL
P11
DP13/PWM8
P12
n.c.
T3
DP24/PWM10 to DP27/PWM13
P14
1
2
3
4
5
6
7
Derivative port line 20 or I
2
C-bus data line.
Port line 10 or I
2
C-bus clock line or emulation input DXWR.
Port line 11 or emulation input DXRD.
Derivative I/O port 13 or PWM8 output.
Port line 12 or emulation input DXALE.
Not connected.
8-bit counter input (Schmitt trigger).
Derivative I/O ports or 8-bit PWM outputs.
Port line 14 or emulation output DXINT.
General I/O port lines.
8, 14, 29, 34
9
10, 12, 13, 15,
17, 18, 19, 20
11
P00 to P07
RSTO
Used for emulation purposes only. This active HIGH output is the
result of the OR operation carried out internally on the RESET
input and the Watchdog Timer reset line.
Not connected.
Ground pin.
Derivative I/O port 11 or ADC channel 1 input.
Derivative I/O ports or 6-bit PWM outputs.
Not connected.
Derivative I/O ports or 7-bit PWM outputs.
Emulation mode control input, normally LOW.
Power supply.
Oscillator input pin for system clock.
Oscillator output pin for system clock.
Not connected.
Reset input; active LOW input initializes device.
Direct testable pin or event counter input.
External interrupt or direct testable pin.
Derivative I/O port 12 or ADC Channel 2 input.
n.c.
V
SS
DP11/ADC1
DP04/PWM4 to DP07/PWM7
n.c.
DP00/PWM0 to DP03/PWM3
EMU
V
DD
XTAL1 (IN)
XTAL2 (OUT)
n.c.
RESET
T1
INTN/T0
DP12/ADC2
16
21
22
25, 24, 23, 42
27
31, 30, 28, 26
32
33
35
36
37
38
39
40
41
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