參數(shù)資料
型號: PCE84C487
廠商: NXP Semiconductors N.V.
英文描述: Microcontrollers for digital auto-sync and VST TV controller applications
中文描述: 微控制器的數(shù)字自動同步和VST電視控制器的應(yīng)用
文件頁數(shù): 22/36頁
文件大?。?/td> 168K
代理商: PCE84C487
1996 Feb 21
22
Philips Semiconductors
Objective specification
Microcontrollers for digital auto-sync and
VST TV controller applications
PCE84C486; PCE84C487
11 WATCHDOG TIMER (WDT)
The purpose of the Watchdog Timer is to reset the
microcontroller, within a reasonable period of time, if it
enters an erroneous processor state. Erroneous processor
states can be caused by noise or RFI.
The Watchdog Timer consists of a 23-bit counter which is
clocked at a frequency of f
osc
. During a Power-on-reset the
contents of the counter are cleared. The counter contents
are then incremented by ‘1’ every oscillator clock cycle.
If the maximum count is exceeded, the counter overflows
and the microcontroller is reset. In order to prevent a
counter overflow and its resulting reset operation, the user
program must clear the contents of the Watchdog Timer
before its maximum count is exceeded. During normal
processing, the contents of the Watchdog Timer are
cleared by writing a logic 1 to Derivative Register 45H (this
is a dummy register).
The maximum time period (t
p
) which the counter may run
and not cause a reset operation, is calculated as shown
below.
In the Idle mode the oscillator is still running and the
Watchdog Timer remains active. In the Stop mode
however, the oscillator is stopped and the operation of the
Watchdog Timer is halted but its contents are retained.
Therefore, it may be advisable for the user to clear the
contents of the Watchdog Timer before the Stop mode is
entered, in order to avoid an unexpected reset operation
after the device is woken-up.
The operational voltage range of the Watchdog Timer is
2 to 5.5 V.
t
p
f
osc
---1
2
22
×
=
Fig.20 The Watchdog Timer.
handbook, full pagewidth
Power-on-reset
WR45H
RESET
CLK
Q22
on-chip RESET
23-BIT COUNTER
fosc
MGC906
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