參數(shù)資料
型號(hào)： PCD5096H
廠商： NXP SEMICONDUCTORS
元件分類： 編解碼器
英文描述： Universal codec
中文描述： A/MU-LAW, PCM CODEC, PQFP44
封裝： 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44
文件頁(yè)數(shù)： 7/52頁(yè)
文件大小： 222K
代理商： PCD5096H
1997 Jan 22
7
Philips Semiconductors
Preliminary specification
Universal codec
PCD5096
6.3
Supply concept
The universal codec is designed for 3 V systems with a voltage range of 2.7 to 3.6 V. To allow connection to 5 V systems
the digital I/Os include level shifters. The core must run on 3.3 V and the peripheral supply on 5 V.
The five power supplies are listed in Table 2. Codec 1 and Codec 2 have their own power supplies: V
DDA_1
and V
DDA_2
respectively. V
DD_PLL
is the power supply dedicated to the PLL. The digital core and the memories are powered by V
DD_2
and the digital peripherals by V
DD_1
. All digital pins (EARP_HF, EARM_HF, TEST, RESET, DI, DO, FSC, DCL, IO0, IO1,
CLK, SCL, SDA, A0 and A1) have internal level shifters, allowing the chip to be used in a 3 to 5 V environment.
Table 2
PCD5096 power supply
SUPPLY PAIR
ASSOCIATED DEVICE
V
DD_1
and V
SS_1
V
DD_2
and V
SS_2
V
DD_PLL
and V
SS_PLL
V
DDA_1
and V
SSA_1
V
DDA_2
and V
SSA_2
3 to 5 V peripheral supply
3 V digital core supply
3 V PLL supply
3 V Codec 1 supply
3 V Codec 2 supply
Fig.3 PCx5096 supply rails with protection diodes.
handbook, full pagewidth
MBH862
VSS_1
VDD_1
VSSA_1
VDDA_1
VSSA_2
VDDA_2
VSS_2
VDD_2
VSS_PLL
VDD_PLL
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