- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄382380 > PCD5096H (NXP SEMICONDUCTORS) Universal codec PDF資料下載
參數(shù)資料
| 型號： | PCD5096H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 編解碼器 |
| 英文描述： | Universal codec |
| 中文描述： | A/MU-LAW, PCM CODEC, PQFP44 |
| 封裝： | 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44 |
| 文件頁數(shù)： | 11/52頁 |
| 文件大?。?/td> | 222K |
| 代理商： | PCD5096H |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁當(dāng)前第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
1997 Jan 22
11
Philips Semiconductors
Preliminary specification
Universal codec
PCD5096
After reset, all the flip-flops are in a defined state, and the
IOM, DSP and codecs are in inactive mode. In typical
applications the universal codec is used with the
PCD5093, which provides a clock (GP_CLK7) and a reset
signal to the universal codec. The reset signal must be
generated by a microcontroller port bit. The RESET_OUT
pin of the PCD5093 cannot be used for this purpose,
because GP_CLK7 is stopped while RESET_OUT is LOW
after a Power-on-reset.
8
MEMORY AND CONTROL REGISTERS
8.1
DSP memories
The DSP in the PCD5096 has access to a 4k
×
24-bit DSP
program ROM, a 512
×
16-bit XRAM and a 512
×
16-bit
YRAM.
8.2
Data memory and control register map
The PCD5096 contains a 128 word (128
×
16-bit) System
Data RAM (SDR) and a group of 7 control registers
mapped onto the upper addresses of the SDR.
The registers and the SDR are byte and word accessible
externally, via the I
2
C-bus interface and internally via the
internal system bus.
The memory map is shown in Fig.6. The lower 32 words
contain the DSP parameter table. The next 32 words are
reserved for the IOM control table, which is used to control
the activity on the IOM-2 interface (maximum 32 slots per
8 kHz speech frame). The rest of the SDR addressable
space (40H to 77H) is free RAM and can be used to store
up to 14 IOM data buffer pairs. In cases where not all
14 IOM buffer pairs are needed this memory space can be
used for other applications via the I
2
C-bus. The same
holds for the unused part of the IOM control table.
The upper addresses of the SDR (78H to 7EH) are
mapped onto 7 control registers (CR0 to CR6) that control
the entire chip (DSP mode, data rate on the IOM-2
interface, control of the two codecs).
Note that the uppermost address of the SDR (7FH) is not
mapped to any hardware register and is addressable as a
normal RAM word.
The contents of the IOM control table and the IOM data
buffers are described in Chapter 9. For further details
about the DSP parameter table, see the “PCD5096 DSP
user manual”
Fig.6 PCD5096 Memory map.
handbook, full pagewidth
MBH865
DSP parameter table
(32 words)
IOM control table
(32 words)
IOM data buffers
and
free RAM
(14 x 4 words)
free RAM
SDR
SDR
hardware registers
00H
1FH
20H
3FH
40H
77H
78H
7EH
7FH
control registers
(7 words)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCD6003 | Digital telephone answering machine chip |
| PCD6003H | Digital telephone answering machine chip |
| PCD6003U | Digital telephone answering machine chip |
| PCD8544 | 48 x 84 pixels matrix LCD controller/driver |
| PCD8544U | 48 x 84 pixels matrix LCD controller/driver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCD5114P | 制造商:NXP Semiconductors 功能描述: |
| PCD-5-R | 功能描述:保險絲 125VAC 5A Radial Lead RoHS:否 制造商:Littelfuse 產(chǎn)品:Surface Mount Fuses 電流額定值:0.5 A 電壓額定值:600 V 保險絲類型:Fast Acting 保險絲大小/組:Nano 尺寸:12.1 mm L x 4.5 mm W 安裝風(fēng)格: 端接類型:SMD/SMT 系列:485 |
| PCD-5-SD | 制造商:COOPER BUSSMANN 功能描述:Fuse Subminiature 5A 125V Fast 2-Pin Radial Through Hole |
| PCD6 | 制造商:LAMBDA 制造商全稱:DENSEI-LAMBDA 功能描述:Single output DC-DC converter 1.5W ~ 6W |
| PCD-60 | 制造商:Pan Pacific 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。